Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom

2023-12-20 15:30:07 -08:00

..

__init__.py

Verilog ROM model created for testing

2023-06-12 15:35:54 -07:00

channel_route.py

Update copyright year

2023-01-28 22:56:27 -08:00

contact.py

Fixed bug that made metal-metal vias think they were well contacts

2023-11-07 14:27:11 -08:00

delay_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

design.py

Merge branch 'char' into STA-refactor

2023-07-19 12:35:22 -07:00

errors.py

Update copyright year

2023-01-28 22:56:27 -08:00

geometry.py

remove line ending whitespace from comment

2023-07-19 10:51:19 -07:00

hierarchy_design.py

get connections from spice objects in instances

2023-07-18 10:50:50 -07:00

hierarchy_layout.py

add parameter to make routing horizonal vdd rails easier

2023-10-31 23:24:21 -07:00

hierarchy_spice.py

cleanup net_spice docstrings

2023-07-19 12:45:41 -07:00

lef.py

implement pin_spice object

2023-07-13 16:45:05 -07:00

logical_effort.py

Update copyright year

2023-01-28 22:56:27 -08:00

pin_layout.py

Update copyright year

2023-01-28 22:56:27 -08:00

power_data.py

Update copyright year

2023-01-28 22:56:27 -08:00

rom_verilog.py

fix for matching the layout vs verilog port names for rom

2023-12-20 15:30:07 -08:00

route.py

Update copyright year

2023-01-28 22:56:27 -08:00

timing_graph.py

Update copyright year

2023-01-28 22:56:27 -08:00

utils.py

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2023-01-28 22:56:27 -08:00

vector3d.py

Update copyright year

2023-01-28 22:56:27 -08:00

vector.py

Update copyright year

2023-01-28 22:56:27 -08:00

verilog.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_path.py

Update copyright year

2023-01-28 22:56:27 -08:00

wire_spice_model.py

add fixme note for unit conversion

2023-06-28 14:05:42 -07:00

wire.py

Update copyright year

2023-01-28 22:56:27 -08:00