mirror of https://github.com/VLSIDA/OpenRAM.git
351 lines
15 KiB
Python
351 lines
15 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import pgate
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import debug
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from tech import drc, parameter, spice
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from vector import vector
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import logical_effort
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from sram_factory import factory
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from globals import OPTS
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import contact
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class pnand3(pgate.pgate):
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"""
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This module generates gds of a parametrically sized 2-input nand.
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This model use ptx to generate a 2-input nand within a cetrain height.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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""" Creates a cell for a simple 3 input nand """
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debug.info(2,
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"creating pnand3 structure {0} with size of {1}".format(name,
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size))
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self.add_comment("size: {}".format(size))
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# We have trouble pitch matching a 3x sizes to the bitcell...
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# If we relax this, we could size this better.
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self.size = size
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self.nmos_size = 2 * size
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self.pmos_size = parameter["beta"] * size
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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# FIXME: Allow these to be sized
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debug.check(size == 1,
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"Size 1 pnand3 is only supported now.")
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self.tx_mults = 1
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if OPTS.tech_name == "sky130":
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self.nmos_width = self.nearest_bin("nmos", self.nmos_width)
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self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
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# Creates the netlist and layout
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pgate.pgate.__init__(self, name, height, add_wells)
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def add_pins(self):
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""" Adds pins for spice netlist """
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pin_list = ["A", "B", "C", "Z", "vdd", "gnd"]
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dir_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
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self.add_pin_list(pin_list, dir_list)
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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self.create_ptx()
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def create_layout(self):
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""" Calls all functions related to the generation of the layout """
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self.setup_layout_constants()
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self.place_ptx()
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if self.add_wells:
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self.add_well_contacts()
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self.route_inputs()
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self.route_output()
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self.determine_width()
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self.route_supply_rails()
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self.connect_rails()
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self.extend_wells()
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self.add_boundary()
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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self.nmos_center = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact="active",
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add_drain_contact="active")
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self.add_mod(self.nmos_center)
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self.nmos_right = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact="active",
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add_drain_contact=self.route_layer)
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self.add_mod(self.nmos_right)
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self.nmos_left = factory.create(module_type="ptx",
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width=self.nmos_width,
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mults=self.tx_mults,
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tx_type="nmos",
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add_source_contact=self.route_layer,
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add_drain_contact="active")
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self.add_mod(self.nmos_left)
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self.pmos_left = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_left)
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self.pmos_center = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_center)
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self.pmos_right = factory.create(module_type="ptx",
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width=self.pmos_width,
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mults=self.tx_mults,
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tx_type="pmos",
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add_source_contact=self.route_layer,
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add_drain_contact=self.route_layer)
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self.add_mod(self.pmos_right)
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def setup_layout_constants(self):
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""" Pre-compute some handy layout parameters. """
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# Compute the overlap of the source and drain pins
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self.ptx_offset = self.pmos_left.get_pin("D").center() - self.pmos_left.get_pin("S").center()
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# This is the extra space needed to ensure DRC rules
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# to the active contacts
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nmos = factory.create(module_type="ptx", tx_type="nmos")
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extra_contact_space = max(-nmos.get_pin("D").by(), 0)
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def create_ptx(self):
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"""
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Create the PMOS and NMOS in the netlist.
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"""
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self.pmos1_inst = self.add_inst(name="pnand3_pmos1",
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mod=self.pmos_left)
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self.connect_inst(["vdd", "A", "Z", "vdd"])
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self.pmos2_inst = self.add_inst(name="pnand3_pmos2",
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mod=self.pmos_center)
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self.connect_inst(["Z", "B", "vdd", "vdd"])
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self.pmos3_inst = self.add_inst(name="pnand3_pmos3",
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mod=self.pmos_right)
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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self.nmos1_inst = self.add_inst(name="pnand3_nmos1",
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mod=self.nmos_left)
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self.connect_inst(["Z", "C", "net1", "gnd"])
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self.nmos2_inst = self.add_inst(name="pnand3_nmos2",
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mod=self.nmos_center)
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self.connect_inst(["net1", "B", "net2", "gnd"])
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self.nmos3_inst = self.add_inst(name="pnand3_nmos3",
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mod=self.nmos_right)
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self.connect_inst(["net2", "A", "gnd", "gnd"])
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def place_ptx(self):
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"""
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Place the PMOS and NMOS in the layout at the upper-most
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and lowest position to provide maximum routing in channel
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"""
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pmos1_pos = vector(self.pmos_left.active_offset.x,
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self.height - self.pmos_left.active_height - self.top_bottom_space)
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self.pmos1_inst.place(pmos1_pos)
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pmos2_pos = pmos1_pos + self.ptx_offset
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self.pmos2_inst.place(pmos2_pos)
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self.pmos3_pos = pmos2_pos + self.ptx_offset
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self.pmos3_inst.place(self.pmos3_pos)
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nmos1_pos = vector(self.pmos_left.active_offset.x,
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self.top_bottom_space)
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self.nmos1_inst.place(nmos1_pos)
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nmos2_pos = nmos1_pos + self.ptx_offset
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self.nmos2_inst.place(nmos2_pos)
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self.nmos3_pos = nmos2_pos + self.ptx_offset
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self.nmos3_inst.place(self.nmos3_pos)
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos_right,
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self.pmos3_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_right,
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self.nmos3_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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self.connect_pin_to_rail(self.nmos1_inst, "S", "gnd")
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self.connect_pin_to_rail(self.pmos1_inst, "S", "vdd")
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self.connect_pin_to_rail(self.pmos2_inst, "D", "vdd")
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def route_inputs(self):
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""" Route the A and B and C inputs """
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# We can use this pitch because the contacts and overlap won't be adjacent
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non_contact_pitch = 0.5 * self.m1_width + self.m1_space + 0.5 * contact.poly_contact.second_layer_height
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pmos_drain_bottom = self.pmos1_inst.get_pin("D").by()
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self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space
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bottom_pin = self.nmos1_inst.get_pin("D")
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# active contact metal to poly contact metal spacing
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active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height
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# active diffusion to poly contact spacing
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# doesn't use nmos uy because that is calculated using offset + poly height
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active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height
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active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height
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active_to_poly_contact2 = active_top + self.poly_contact_to_gate + 0.5 * self.route_layer_width
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self.inputA_yoffset = max(active_contact_to_poly_contact,
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active_to_poly_contact,
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active_to_poly_contact2)
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apin = self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="left")
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self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch
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bpin = self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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self.inputB_yoffset,
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"B",
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position="center")
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self.inputC_yoffset = self.inputB_yoffset + self.m3_pitch
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cpin = self.route_input_gate(self.pmos3_inst,
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self.nmos3_inst,
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self.inputC_yoffset,
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"C",
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position="right")
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if OPTS.tech_name == "sky130":
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self.add_enclosure([apin, bpin, cpin], "npc", drc("npc_enclose_poly"))
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos1_pin = self.pmos1_inst.get_pin("D")
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# PMOS3 drain
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pmos3_pin = self.pmos3_inst.get_pin("D")
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# NMOS3 drain
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nmos3_pin = self.nmos3_inst.get_pin("D")
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out_offset = vector(nmos3_pin.cx() + self.route_layer_pitch,
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self.output_yoffset)
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# Go up to metal2 for ease on all output pins
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos1_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos3_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=nmos3_pin.center(),
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# directions=("V", "V"))
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# # Route in the A input track (top track)
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# mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
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# self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
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# This extends the output to the edge of the cell
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# self.add_via_center(layers=self.m1_stack,
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# offset=mid_offset)
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top_left_pin_offset = pmos1_pin.center()
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top_right_pin_offset = pmos3_pin.center()
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bottom_pin_offset = nmos3_pin.center()
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# PMOS1 to output
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self.add_path(self.route_layer, [top_left_pin_offset,
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vector(top_left_pin_offset.x, out_offset.y),
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out_offset])
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# PMOS3 to output
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self.add_path(self.route_layer, [top_right_pin_offset,
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vector(top_right_pin_offset.x, out_offset.y),
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out_offset])
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# NMOS3 to output
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mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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self.add_path(self.route_layer,
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[bottom_pin_offset, mid2_offset],
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width=nmos3_pin.height())
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mid3_offset = vector(out_offset.x, nmos3_pin.by())
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self.add_path(self.route_layer, [mid3_offset, out_offset])
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self.add_layout_pin_rect_center(text="Z",
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layer=self.route_layer,
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offset=out_offset)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_frequency"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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c_load = load
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1094
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return transition_prob * (c_load + c_para)
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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return self.nmos_size + self.pmos_size
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def get_stage_effort(self, cout, inp_is_rise=True):
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"""
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Returns an object representing the parameters for delay in tau units.
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Optional is_rise refers to the input direction rise/fall.
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Input inverted by this stage.
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"""
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parasitic_delay = 3
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return logical_effort.logical_effort(self.name,
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self.size,
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self.input_load(),
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cout,
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parasitic_delay,
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not inp_is_rise)
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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