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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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9a6b38b67efb27307cec17f61bf8ecfe9c7d72e7
OpenRAM/compiler/pgates
T
History
Joey Kunzler 9a6b38b67e merge conflict
2020-05-26 16:03:36 -07:00
..
pand2.py
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
pand3.py
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
pbuf.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pdriver.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
pgate.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
pinv.py
Check min size inverter.
2020-05-13 16:54:26 -07:00
pinvbuf.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
pnand2.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
pnand3.py
Determine width after routing with no well contacts.
2020-05-13 16:04:38 -07:00
pnor2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
precharge.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptristate_inv.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptx.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
pwrite_driver.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
single_level_column_mux.py
merge conflict
2020-05-26 16:03:36 -07:00
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