mirror of https://github.com/VLSIDA/OpenRAM.git
77 lines
4.0 KiB
Plaintext
77 lines
4.0 KiB
Plaintext
[globals/init_openram]: Initializing OpenRAM...
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[globals/setup_paths]: Setting up paths...
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[globals/setup_paths]: Temporary files saved in /home/jesse/output/
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[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
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[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
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[globals/import_tech]: Importing technology: s8
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[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
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[globals/init_paths]: Creating temp directory: /home/jesse/output/
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[verify/<module>]: Initializing verify...
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[verify/<module>]: Finding DRC/LVS/PEX tools.
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[globals/get_tool]: Finding DRC tool...
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[globals/get_tool]: Using DRC: /usr/local/bin/magic
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[globals/get_tool]: Finding LVS tool...
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[globals/get_tool]: Using LVS: /usr/local/bin/netgen
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[globals/get_tool]: Finding PEX tool...
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[globals/get_tool]: Using PEX: /usr/local/bin/magic
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[characterizer/<module>]: Initializing characterizer...
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[characterizer/<module>]: Finding spice simulator.
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[globals/get_tool]: Finding spice tool...
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[globals/get_tool]: Could not find hspice, trying next spice tool.
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[globals/get_tool]: Using spice: /usr/local/bin/ngspice
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[globals/setup_bitcell]: Using bitcell: bitcell
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|==============================================================================|
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|========= OpenRAM v1.1.4 =========|
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|========= =========|
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|========= VLSI Design and Automation Lab =========|
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|========= Computer Science and Engineering Department =========|
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|========= University of California Santa Cruz =========|
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|========= =========|
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|========= Usage help: openram-user-group@ucsc.edu =========|
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|========= Development help: openram-dev-group@ucsc.edu =========|
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|========= Temp dir: /home/jesse/output/ =========|
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|========= See LICENSE for license info =========|
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|==============================================================================|
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** Start: 04/18/2020 04:50:34
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Technology: s8
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Total size: 32 bits
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Word size: 2
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Words: 16
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Banks: 1
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Write size: None
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RW ports: 1
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R-only ports: 0
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W-only ports: 0
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DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
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Performing simulation-based characterization with ngspice
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[bitcell/__init__]: Create bitcell
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[sram_config/recompute_sizes]: Recomputing with words per row: 1
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[sram_config/recompute_sizes]: Rows: 16 Cols: 2
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[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
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Words per row: 1
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Output files are:
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/home/jesse/openram/compiler/temp/sram_2_16_s8.sp
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/home/jesse/openram/compiler/temp/sram_2_16_s8.v
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/home/jesse/openram/compiler/temp/sram_2_16_s8.lib
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/home/jesse/openram/compiler/temp/sram_2_16_s8.py
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/home/jesse/openram/compiler/temp/sram_2_16_s8.html
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/home/jesse/openram/compiler/temp/sram_2_16_s8.log
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/home/jesse/openram/compiler/temp/sram_2_16_s8.lef
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/home/jesse/openram/compiler/temp/sram_2_16_s8.gds
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[sram/__init__]: create sram of size 2 with 16 num of words 1 banks
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[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
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[dff_array/__init__]: Creating data_dff rows=1 cols=2
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[bank/__init__]: create sram of size 2 with 16 words
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[port_data/__init__]: create data port of size 2 with 1 words per row
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[precharge/__init__]: creating precharge cell precharge_0
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[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
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[precharge_array/__init__]: Creating precharge_array_0
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[precharge/__init__]: creating precharge cell precharge_1
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[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
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[sense_amp_array/__init__]: Creating sense_amp_array_0
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[sense_amp/__init__]: Create sense_amp
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[write_driver_array/__init__]: Creating write_driver_array_0
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[write_driver/__init__]: Create write_driver
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ERROR: file hierarchy_layout.py: line 1092: Cyclic VCG in channel router.
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