mirror of https://github.com/VLSIDA/OpenRAM.git
102 lines
2.9 KiB
Python
Executable File
102 lines
2.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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"""
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SRAM Compiler
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The output files append the given suffixes to the output name:
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a spice (.sp) file for circuit simulation
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a GDS2 (.gds) file containing the layout
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a LEF (.lef) file for preliminary P&R (real one should be from layout)
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a Liberty (.lib) file for timing analysis/optimization
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"""
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import os
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import sys
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import datetime
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try:
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import openram
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except:
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# If openram library isn't found as a python package,
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# import it from the $OPENRAM_HOME path.
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import importlib.util
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OPENRAM_HOME = os.getenv("OPENRAM_HOME")
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# Import using spec since the directory can be named something
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# other than "openram".
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spec = importlib.util.spec_from_file_location("openram", "{}/../__init__.py".format(OPENRAM_HOME))
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module = importlib.util.module_from_spec(spec)
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sys.modules["openram"] = module
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spec.loader.exec_module(module)
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import openram
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(OPTS, args) = openram.parse_args()
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# Check that we are left with a single configuration file as argument.
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if len(args) != 1:
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print(openram.USAGE)
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sys.exit(2)
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# These depend on arguments, so don't load them until now.
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import debug
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# Parse config file and set up all the options
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openram.init_openram(config_file=args[0], is_unit_test=False)
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# Ensure that the right bitcell exists or use the parameterised one
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openram.setup_bitcell()
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# Only print banner here so it's not in unit tests
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openram.print_banner()
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# Keep track of running stats
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start_time = datetime.datetime.now()
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openram.print_time("Start", start_time)
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# Output info about this run
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openram.report_status()
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from modules import sram_config
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# Configure the SRAM organization
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c = sram_config(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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write_size=OPTS.write_size,
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num_banks=OPTS.num_banks,
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words_per_row=OPTS.words_per_row,
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num_spare_rows=OPTS.num_spare_rows,
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num_spare_cols=OPTS.num_spare_cols)
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debug.print_raw("Words per row: {}".format(c.words_per_row))
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output_extensions = ["lvs", "sp", "v", "lib", "py", "html", "log"]
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# Only output lef/gds if back-end
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if not OPTS.netlist_only:
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output_extensions.extend(["lef", "gds"])
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output_files = ["{0}{1}.{2}".format(OPTS.output_path,
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OPTS.output_name, x)
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for x in output_extensions]
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debug.print_raw("Output files are: ")
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for path in output_files:
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debug.print_raw(path)
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from modules import sram
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s = sram(name=OPTS.output_name,
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sram_config=c)
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# Output the files for the resulting SRAM
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s.save()
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# Delete temp files etc.
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openram.end_openram()
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openram.print_time("End", datetime.datetime.now(), start_time)
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