mirror of https://github.com/VLSIDA/OpenRAM.git
444 lines
19 KiB
Python
444 lines
19 KiB
Python
import sys
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import datetime
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import getpass
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import debug
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from math import log,sqrt,ceil
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from vector import vector
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from globals import OPTS, print_time
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from design import design
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class sram_base(design):
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"""
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Dynamically generated SRAM by connecting banks to control logic. The
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number of banks should be 1 , 2 or 4
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"""
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def __init__(self, word_size, num_words, num_banks, name):
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design.__init__(self, name)
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from importlib import reload
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c = reload(__import__(OPTS.control_logic))
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self.mod_control_logic = getattr(c, OPTS.control_logic)
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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c = reload(__import__(OPTS.ms_flop))
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self.mod_ms_flop = getattr(c, OPTS.ms_flop)
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self.ms_flop = self.mod_ms_flop()
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self.word_size = word_size
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self.num_words = num_words
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self.num_banks = num_banks
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def compute_sizes(self):
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""" Computes the organization of the memory using bitcell size by trying to make it square."""
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debug.check(self.num_banks in [1,2,4], "Valid number of banks are 1 , 2 and 4.")
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self.num_words_per_bank = self.num_words/self.num_banks
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self.num_bits_per_bank = self.word_size*self.num_words_per_bank
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# Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry)
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self.bank_area = self.bitcell.width*self.bitcell.height*self.num_bits_per_bank
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self.bank_side_length = sqrt(self.bank_area)
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# Estimate the words per row given the height of the bitcell and the square side length
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self.tentative_num_cols = int(self.bank_side_length/self.bitcell.width)
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self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size)
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# Estimate the number of rows given the tentative words per row
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self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row*self.word_size)
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self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
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# Fix the number of columns and rows
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self.num_cols = int(self.words_per_row*self.word_size)
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self.num_rows = int(self.num_words_per_bank/self.words_per_row)
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# Compute the address and bank sizes
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self.row_addr_size = int(log(self.num_rows, 2))
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self.col_addr_size = int(log(self.words_per_row, 2))
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self.bank_addr_size = self.col_addr_size + self.row_addr_size
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self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
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debug.info(1,"Words per row: {}".format(self.words_per_row))
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def estimate_words_per_row(self,tentative_num_cols, word_size):
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"""
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This provides a heuristic rounded estimate for the number of words
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per row.
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"""
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if tentative_num_cols < 1.5*word_size:
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return 1
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elif tentative_num_cols > 3*word_size:
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return 4
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else:
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return 2
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def amend_words_per_row(self,tentative_num_rows, words_per_row):
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"""
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This picks the number of words per row more accurately by limiting
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it to a minimum and maximum.
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"""
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# Recompute the words per row given a hard max
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if(tentative_num_rows > 512):
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debug.check(tentative_num_rows*words_per_row <= 2048, "Number of words exceeds 2048")
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return int(words_per_row*tentative_num_rows/512)
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# Recompute the words per row given a hard min
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if(tentative_num_rows < 16):
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debug.check(tentative_num_rows*words_per_row >= 16, "Minimum number of rows is 16, but given {0}".format(tentative_num_rows))
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return int(words_per_row*tentative_num_rows/16)
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return words_per_row
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def add_pins(self):
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""" Add pins for entire SRAM. """
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for i in range(self.word_size):
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self.add_pin("DIN[{0}]".format(i),"INPUT")
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for i in range(self.addr_size):
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self.add_pin("ADDR[{0}]".format(i),"INPUT")
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# These are used to create the physical pins too
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self.control_logic_inputs=self.control_logic.get_inputs()
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self.control_logic_outputs=self.control_logic.get_outputs()
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self.add_pin_list(self.control_logic_inputs,"INPUT")
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for i in range(self.word_size):
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self.add_pin("DOUT[{0}]".format(i),"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def create_layout(self):
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""" Layout creation """
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self.add_modules()
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self.route()
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self.add_lvs_correspondence_points()
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def compute_bus_sizes(self):
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""" Compute the independent bus widths shared between two and four bank SRAMs """
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# address size + control signals + one-hot bank select signals
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self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks,2) + 1
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# data bus size
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self.num_horizontal_line = self.word_size
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self.vertical_bus_width = self.m2_pitch*self.num_vertical_line
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# vertical bus height depends on 2 or 4 banks
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self.data_bus_height = self.m3_pitch*self.num_horizontal_line
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self.data_bus_width = 2*(self.bank.width + self.bank_to_bus_distance) + self.vertical_bus_width
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self.control_bus_height = self.m1_pitch*(self.control_size+2)
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self.control_bus_width = self.bank.width + self.bank_to_bus_distance + self.vertical_bus_width
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self.supply_bus_height = self.m1_pitch*2 # 2 for vdd/gnd placed with control bus
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self.supply_bus_width = self.data_bus_width
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# Sanity check to ensure we can fit the control logic above a single bank (0.9 is a hack really)
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debug.check(self.bank.width + self.vertical_bus_width > 0.9*self.control_logic.width,
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"Bank is too small compared to control logic.")
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def add_busses(self):
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""" Add the horizontal and vertical busses """
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# Vertical bus
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# The order of the control signals on the control bus:
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self.control_bus_names = ["clk_buf", "tri_en_bar", "tri_en", "clk_buf_bar", "w_en", "s_en"]
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self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=self.vertical_bus_offset,
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names=self.control_bus_names,
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length=self.vertical_bus_height)
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self.addr_bus_names=["A[{}]".format(i) for i in range(self.addr_size)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=self.addr_bus_offset,
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names=self.addr_bus_names,
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length=self.addr_bus_height))
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self.bank_sel_bus_names = ["bank_sel[{}]".format(i) for i in range(self.num_banks)]
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self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=self.bank_sel_bus_offset,
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names=self.bank_sel_bus_names,
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length=self.vertical_bus_height))
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# Horizontal data bus
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self.data_bus_names = ["DATA[{}]".format(i) for i in range(self.word_size)]
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self.data_bus_positions = self.create_horizontal_pin_bus(layer="metal3",
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pitch=self.m3_pitch,
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offset=self.data_bus_offset,
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names=self.data_bus_names,
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length=self.data_bus_width)
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# Horizontal control logic bus
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# vdd/gnd in bus go along whole SRAM
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# FIXME: Fatten these wires?
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self.horz_control_bus_positions = self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.supply_bus_offset,
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names=["vdd"],
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length=self.supply_bus_width)
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# The gnd rail must not be the entire width since we protrude the right-most vdd rail up for
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# the decoder in 4-bank SRAMs
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self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.supply_bus_offset+vector(0,self.m1_pitch),
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names=["gnd"],
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length=self.supply_bus_width))
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self.horz_control_bus_positions.update(self.create_horizontal_bus(layer="metal1",
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pitch=self.m1_pitch,
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offset=self.control_bus_offset,
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names=self.control_bus_names,
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length=self.control_bus_width))
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def route_vdd_gnd(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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# These are the instances that every bank has
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top_instances = [self.bitcell_array_inst,
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self.precharge_array_inst,
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self.sense_amp_array_inst,
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self.write_driver_array_inst,
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self.tri_gate_array_inst,
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self.row_decoder_inst,
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self.wordline_driver_inst]
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# Add these if we use the part...
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if self.col_addr_size > 0:
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top_instances.append(self.col_decoder_inst)
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top_instances.append(self.col_mux_array_inst)
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if self.num_banks > 1:
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top_instances.append(self.bank_select_inst)
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for inst in top_instances:
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# Column mux has no vdd
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if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst):
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self.copy_layout_pin(inst, "vdd")
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# Precharge has no gnd
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if inst != self.precharge_array_inst:
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self.copy_layout_pin(inst, "gnd")
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def create_multi_bank_modules(self):
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""" Create the multibank address flops and bank decoder """
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from dff_buf_array import dff_buf_array
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self.msb_address = dff_buf_array(name="msb_address",
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rows=1,
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columns=self.num_banks/2)
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self.add_mod(self.msb_address)
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if self.num_banks>2:
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self.msb_decoder = self.bank.decoder.pre2_4
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self.add_mod(self.msb_decoder)
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def create_modules(self):
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""" Create all the modules that will be used """
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from control_logic import control_logic
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# Create the control logic module
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self.control_logic = self.mod_control_logic(num_rows=self.num_rows)
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self.add_mod(self.control_logic)
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# Create the address and control flops (but not the clk)
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from dff_array import dff_array
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self.row_addr_dff = dff_array(name="row_addr_dff", rows=self.row_addr_size, columns=1)
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self.add_mod(self.row_addr_dff)
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if self.col_addr_size > 0:
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self.col_addr_dff = dff_array(name="col_addr_dff", rows=1, columns=self.col_addr_size)
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self.add_mod(self.col_addr_dff)
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else:
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self.col_addr_dff = None
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self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size)
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self.add_mod(self.data_dff)
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# Create the bank module (up to four are instantiated)
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from bank import bank
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self.bank = bank(word_size=self.word_size,
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num_words=self.num_words_per_bank,
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words_per_row=self.words_per_row,
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num_banks=self.num_banks,
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name="bank")
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self.add_mod(self.bank)
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# Create bank decoder
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if(self.num_banks > 1):
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self.create_multi_bank_modules()
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self.bank_count = 0
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self.supply_rail_width = self.bank.supply_rail_width
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self.supply_rail_pitch = self.bank.supply_rail_pitch
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def add_bank(self, bank_num, position, x_flip, y_flip):
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""" Place a bank at the given position with orientations """
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# x_flip == 1 --> no flip in x_axis
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# x_flip == -1 --> flip in x_axis
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# y_flip == 1 --> no flip in y_axis
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# y_flip == -1 --> flip in y_axis
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# x_flip and y_flip are used for position translation
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if x_flip == -1 and y_flip == -1:
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bank_rotation = 180
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else:
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bank_rotation = 0
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if x_flip == y_flip:
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bank_mirror = "R0"
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elif x_flip == -1:
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bank_mirror = "MX"
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elif y_flip == -1:
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bank_mirror = "MY"
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else:
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bank_mirror = "R0"
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bank_inst=self.add_inst(name="bank{0}".format(bank_num),
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mod=self.bank,
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offset=position,
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mirror=bank_mirror,
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rotate=bank_rotation)
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temp = []
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for i in range(self.word_size):
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temp.append("DOUT[{0}]".format(i))
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for i in range(self.word_size):
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temp.append("BANK_DIN[{0}]".format(i))
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for i in range(self.bank_addr_size):
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temp.append("A[{0}]".format(i))
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if(self.num_banks > 1):
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temp.append("bank_sel[{0}]".format(bank_num))
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temp.extend(["s_en", "w_en", "tri_en_bar", "tri_en",
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"clk_buf_bar","clk_buf" , "vdd", "gnd"])
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self.connect_inst(temp)
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return bank_inst
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def add_row_addr_dff(self, position):
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""" Add and place all address flops for the main decoder """
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self.row_addr_dff_inst = self.add_inst(name="row_address",
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mod=self.row_addr_dff,
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offset=position)
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# inputs, outputs/output/bar
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inputs = []
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outputs = []
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for i in range(self.row_addr_size):
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inputs.append("ADDR[{}]".format(i+self.col_addr_size))
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outputs.append("A[{}]".format(i+self.col_addr_size))
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# FIXME clk->clk_buf
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self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
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def add_col_addr_dff(self, position):
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""" Add and place all address flops for the column decoder """
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self.col_addr_dff_inst = self.add_inst(name="row_address",
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mod=self.col_addr_dff,
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offset=position)
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# inputs, outputs/output/bar
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inputs = []
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outputs = []
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for i in range(self.col_addr_size):
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inputs.append("ADDR[{}]".format(i))
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outputs.append("A[{}]".format(i))
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# FIXME clk->clk_buf
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self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
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def add_data_dff(self, position):
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""" Add and place all data flops """
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self.data_dff_inst = self.add_inst(name="data_dff",
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mod=self.data_dff,
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offset=position)
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# inputs, outputs/output/bar
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inputs = []
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outputs = []
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for i in range(self.word_size):
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inputs.append("DIN[{}]".format(i))
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outputs.append("BANK_DIN[{}]".format(i))
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# FIXME clk->clk_buf_bar
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self.connect_inst(inputs + outputs + ["clk", "vdd", "gnd"])
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def add_control_logic(self, position):
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""" Add and place control logic """
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self.control_logic_inst=self.add_inst(name="control",
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mod=self.control_logic,
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offset=position)
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self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"])
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def connect_rail_from_left_m2m3(self, src_pin, dest_pin):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pos = src_pin.rc()
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out_pos = dest_pin.center()
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self.add_wire(("metal3","via2","metal2"),[in_pos, vector(out_pos.x,in_pos.y),out_pos])
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=src_pin.rc(),
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rotate=90)
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def connect_rail_from_left_m2m1(self, src_pin, dest_pin):
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""" Helper routine to connect an unrotated/mirrored oriented instance to the rails """
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in_pos = src_pin.rc()
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out_pos = vector(dest_pin.cx(), in_pos.y)
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self.add_wire(("metal2","via1","metal1"),[in_pos, out_pos, out_pos - vector(0,self.m2_pitch)])
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def sp_write(self, sp_name):
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# Write the entire spice of the object to the file
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############################################################
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# Spice circuit
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############################################################
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sp = open(sp_name, 'w')
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sp.write("**************************************************\n")
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sp.write("* OpenRAM generated memory.\n")
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sp.write("* Words: {}\n".format(self.num_words))
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sp.write("* Data bits: {}\n".format(self.word_size))
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sp.write("* Banks: {}\n".format(self.num_banks))
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sp.write("* Column mux: {}:1\n".format(self.words_per_row))
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sp.write("**************************************************\n")
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# This causes unit test mismatch
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# sp.write("* Created: {0}\n".format(datetime.datetime.now()))
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# sp.write("* User: {0}\n".format(getpass.getuser()))
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# sp.write(".global {0} {1}\n".format(spice["vdd_name"],
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# spice["gnd_name"]))
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usedMODS = list()
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self.sp_write_file(sp, usedMODS)
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del usedMODS
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sp.close()
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def analytical_delay(self,slew,load):
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""" LH and HL are the same in analytical model. """
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return self.bank.analytical_delay(slew,load)
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