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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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97fc37aec1be392cb26a8a8cd4aae70bbb6338b8
OpenRAM/technology/freepdk45
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Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
..
gds_lib
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sp_lib
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
tech
Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
tf
Change layer text to comment to avoid glade reserved keyword
2018-11-02 10:58:00 -07:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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