mirror of https://github.com/VLSIDA/OpenRAM.git
353 lines
13 KiB
Python
353 lines
13 KiB
Python
import os
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from design_rules import *
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"""
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File containing the process technology parameters for FreePDK 45nm.
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"""
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#GDS file info
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GDS = {}
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# gds units
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GDS["unit"] = (0.0005,1e-9)
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# default label zoom
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GDS["zoom"] = 0.05
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###################################################
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##GDS Layer Map
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###################################################
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# create the GDS layer map
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# FIXME: parse the gds layer map from the cadence map?
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layer = {}
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layer["active"] = 1
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layer["pwell"] = 2
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layer["nwell"] = 3
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layer["nimplant"]= 4
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layer["pimplant"]= 5
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layer["vtg"] = 6
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layer["vth"] = 7
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layer["thkox"] = 8
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layer["poly"] = 9
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layer["contact"] = 10
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layer["active_contact"] = 10
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layer["metal1"] = 11
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layer["via1"] = 12
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layer["metal2"] = 13
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layer["via2"] = 14
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layer["metal3"] = 15
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layer["via3"] = 16
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layer["metal4"] = 17
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layer["via4"] = 18
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layer["metal5"] = 19
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layer["via5"] = 20
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layer["metal6"] = 21
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layer["via6"] = 22
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layer["metal7"] = 23
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layer["via7"] = 24
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layer["metal8"] = 25
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layer["via8"] = 26
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layer["metal9"] = 27
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layer["via9"] = 28
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layer["metal10"] = 29
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layer["text"] = 239
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layer["boundary"]= 239
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layer["blockage"]= 239
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
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###################################################
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 0.09
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parameter["beta"] = 3
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parameter["6T_inv_nmos_size"] = 0.205
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parameter["6T_inv_pmos_size"] = 0.09
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parameter["6T_access_size"] = 0.135
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc = design_rules("freepdk45")
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drc["body_tie_down"] = 0
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drc["has_pwell"] = True
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drc["has_nwell"] = True
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#grid size
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drc["grid"] = 0.0025
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS.rul"
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drc["xrc_rules"]=drclvs_home+"/calibrexRC.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/freepdk45/layers.map"
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"] = 0.09
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drc["minlength_channel"] = 0.05
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# WELL.2 Minimum spacing of nwell/pwell at different potential
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drc["pwell_to_nwell"] = 0.225
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# WELL.3 Minimum spacing of nwell/pwell at the same potential
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drc["well_to_well"] = 0.135
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# WELL.4 Minimum width of nwell/pwell
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drc["minwidth_well"] = 0.2
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# POLY.1 Minimum width of poly
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drc["minwidth_poly"] = 0.05
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# POLY.2 Minimum spacing of poly AND active
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drc["poly_to_poly"] = 0.14
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# POLY.3 Minimum poly extension beyond active
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drc["poly_extend_active"] = 0.055
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# Not a rule
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drc["poly_to_polycontact"] = 0.075
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# POLY.4 Minimum enclosure of active around gate
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drc["active_enclosure_gate"] = 0.07
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# POLY.5 Minimum spacing of field poly to active
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drc["poly_to_active"] = 0.05
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# POLY.6 Minimum Minimum spacing of field poly
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drc["poly_to_field_poly"] = 0.075
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# Not a rule
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drc["minarea_poly"] = 0.0
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# ACTIVE.2 Minimum spacing of active
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drc["active_to_body_active"] = 0.08
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# ACTIVE.1 Minimum width of active
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drc["minwidth_active"] = 0.09
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# Not a rule
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drc["active_to_active"] = 0
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# ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
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drc["well_enclosure_active"] = 0.055
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 0.055
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# Not a rule
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drc["minarea_active"] = 0
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# IMPLANT.1 Minimum spacing of nimplant/ pimplant to channel
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drc["implant_to_channel"] = 0.07
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# Not a rule
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drc["implant_enclosure_active"] = 0
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# Not a rule
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drc["implant_enclosure_contact"] = 0
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# IMPLANT.2 Minimum spacing of nimplant/ pimplant to contact
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drc["implant_to_contact"] = 0.025
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# IMPLANT.3 Minimum width/ spacing of nimplant/ pimplant
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drc["implant_to_implant"] = 0.045
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# IMPLANT.4 Minimum width/ spacing of nimplant/ pimplant
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drc["minwidth_implant"] = 0.045
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# CONTACT.1 Minimum width of contact
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drc["minwidth_contact"] = 0.065
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# CONTACT.2 Minimum spacing of contact
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drc["contact_to_contact"] = 0.075
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# CONTACT.4 Minimum enclosure of active around contact
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drc["active_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["active_extend_contact"] = 0.005
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# CONTACT.5 Minimum enclosure of poly around contact
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drc["poly_enclosure_contact"] = 0.005
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.005
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# CONTACT.6 Minimum spacing of contact and gate
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drc["contact_to_gate"] = 0.0375 #changed from 0.035
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# CONTACT.7 Minimum spacing of contact and poly
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drc["contact_to_poly"] = 0.090
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# METAL1.1 Minimum width of metal1
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drc["minwidth_metal1"] = 0.065
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# METAL1.2 Minimum spacing of metal1
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drc["metal1_to_metal1"] = 0.065
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# METAL1.3 Minimum enclosure around contact on two opposite sides
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drc["metal1_enclosure_contact"] = 0
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# Reserved for asymmetric enclosures
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drc["metal1_extend_contact"] = 0.035
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# METAL1.4 inimum enclosure around via1 on two opposite sides
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drc["metal1_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal1_enclosure_via1"] = 0
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# Not a rule
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drc["minarea_metal1"] = 0
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# VIA1.1 Minimum width of via1
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drc["minwidth_via1"] = 0.065
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# VIA1.2 Minimum spacing of via1
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drc["via1_to_via1"] = 0.075
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal2"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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drc["metal2_to_metal2"] = 0.07
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal2_extend_via1"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal2_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0
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# Not a rule
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drc["minarea_metal2"] = 0
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via2"] = 0.065
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via2_to_via2"] = 0.075
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# METALINT.1 Minimum width of intermediate metal
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drc["minwidth_metal3"] = 0.07
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# METALINT.2 Minimum spacing of intermediate metal
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#drc["metal3_to_metal3"] = 0.07
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# Minimum spacing of metal3 wider than 0.09 & longer than 0.3 = 0.09
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# Minimum spacing of metal3 wider than 0.27 & longer than 0.9 = 0.27
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# Minimum spacing of metal3 wider than 0.5 & longer than 1.8 = 0.5
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# Minimum spacing of metal3 wider than 0.9 & longer than 2.7 = 0.9
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# Minimum spacing of metal3 wider than 1.5 & longer than 4.0 = 1.5
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drc["metal3_to_metal3"] = drc_lut({(0.00, 0.0) : 0.07,
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(0.09, 0.3) : 0.09,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5})
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# METALINT.3 Minimum enclosure around via1 on two opposite sides
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drc["metal3_extend_via2"] = 0.035
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 0
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# METALINT.4 Minimum enclosure around via[2-3] on two opposite sides
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drc["metal3_extend_via3"]=0.035
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via3"] = 0
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# Not a rule
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drc["minarea_metal3"] = 0
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# VIA2-3.1 Minimum width of Via[2-3]
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drc["minwidth_via3"] = 0.07
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# VIA2-3.2 Minimum spacing of Via[2-3]
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drc["via3_to_via3"] = 0.085
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# METALSMG.1 Minimum width of semi-global metal
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drc["minwidth_metal4"] = 0.14
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# METALSMG.2 Minimum spacing of semi-global metal
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#drc["metal4_to_metal4"] = 0.14
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# Minimum spacing of metal4 wider than 0.27 & longer than 0.9 = 0.27
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# Minimum spacing of metal4 wider than 0.5 & longer than 1.8 = 0.5
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# Minimum spacing of metal4 wider than 0.9 & longer than 2.7 = 0.9
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# Minimum spacing of metal4 wider than 1.5 & longer than 4.0 = 1.5
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drc["metal4_to_metal4"] = drc_lut({(0.00, 0.0) : 0.14,
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(0.27, 0.9) : 0.27,
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(0.50, 1.8) : 0.5,
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(0.90, 2.7) : 0.9,
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(1.50, 4.0) : 1.5})
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# METALSMG.3 Minimum enclosure around via[3-6] on two opposite sides
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drc["metal4_extend_via3"] = 0.0025
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# Reserved for asymmetric enclosure
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drc["metal4_enclosure_via3"] = 0.0025
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# Not a rule
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drc["minarea_metal4"] = 0
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# Metal 5-10 are ommitted
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###################################################
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##END DRC/LVS Rules
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###################################################
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###################################################
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##Spice Simulation Parameters
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###################################################
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#spice info
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spice = {}
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spice["nmos"] = "nmos_vtg"
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spice["pmos"] = "pmos_vtg"
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# This is a map of corners to model files
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SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
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spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"],
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"FF" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"],
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"SF" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"],
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"FS" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"],
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"SS" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"],
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"ST" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"],
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"TS" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"],
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"FT" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"],
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"TF" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"],
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}
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#spice stimulus related variables
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spice["feasible_period"] = 5 # estimated feasible period in ns
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spice["supply_voltages"] = [0.9, 1.0, 1.1] # Supply voltage corners in [Volts]
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spice["nom_supply_voltage"] = 1.0 # Nominal supply voltage in [Volts]
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spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
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spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
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spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
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spice["nom_temperature"] = 25 # Nominal temperature (celcius)
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#sram signal names
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#FIXME: We don't use these everywhere...
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spice["vdd_name"] = "vdd"
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spice["gnd_name"] = "gnd"
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spice["control_signals"] = ["CSB", "WEB"]
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spice["data_name"] = "DATA"
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spice["addr_name"] = "ADDR"
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spice["minwidth_tx"] = drc["minwidth_tx"]
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spice["channel"] = drc["minlength_channel"]
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spice["clk"] = "clk"
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# analytical delay parameters
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spice["vdd_nominal"] = 1.0 # Typical Threshold voltage in Volts
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spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts
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spice["v_threshold_typical"] = 0.4 # Typical Threshold voltage in Volts
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spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
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spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
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spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
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spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
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spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
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spice["msflop_setup"] = 9 # DFF setup time in ps
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spice["msflop_hold"] = 1 # DFF hold time in ps
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spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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spice["dff_setup"] = 9 # DFF setup time in ps
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spice["dff_hold"] = 1 # DFF hold time in ps
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spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["dff_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
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# analytical power parameters, many values are temporary
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spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
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spice["inv_leakage"] = 1 # Leakage power of inverter in nW
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spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
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spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
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spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
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spice["msflop_leakage"] = 1 # Leakage power of flop in nW
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spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
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spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
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spice["flop_transition_prob"] = .5 # Transition probability of inverter.
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spice["inv_transition_prob"] = .5 # Transition probability of inverter.
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spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand.
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spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand.
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spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
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#Parameters related to sense amp enable timing and delay chain/RBL sizing
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parameter["static_delay_stages"] = 4
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parameter["static_fanout_per_stage"] = 3
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parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
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parameter["dff_clk_cin"] = 30.6 #relative capacitance
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parameter["6tcell_wl_cin"] = 3 #relative capacitance
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parameter["min_inv_para_delay"] = 2.4 #Tau delay units
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parameter["sa_en_pmos_size"] = .72 #micro-meters
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parameter["sa_en_nmos_size"] = .27 #micro-meters
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parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
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###################################################
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##END Spice Simulation Parameters
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###################################################
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