OpenRAM/compiler/bitcells
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
..
bitcell_1port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
bitcell_2port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
bitcell_base.py Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
col_cap_bitcell_2port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
dummy_bitcell_1port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
dummy_bitcell_2port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
dummy_pbitcell.py Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
pbitcell.py Fix various typos and errors 2020-11-13 16:04:07 -08:00
replica_bitcell_1port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
replica_bitcell_2port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
replica_pbitcell.py Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
row_cap_bitcell_2port.py Update property settings with getters/setters 2020-11-14 08:08:42 -08:00