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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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93c6565b66bf1124b68a2a2fc62e9cdb2c52809c
OpenRAM/compiler/sram
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mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
..
sram_1bank.py
Add extra dnwell spacing for single port
2021-06-23 11:14:58 -07:00
sram_2bank.py
Update copyright year.
2021-01-22 11:23:28 -08:00
sram_base.py
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
sram_config.py
Add str function for sram_config
2021-09-07 16:49:31 -07:00
sram.py
Add technology parameter for library prefix during uniquification of GDS
2021-07-12 11:01:51 -07:00
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