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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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922e3f4c137da3004099ced7c641cbd2c98d9d99
OpenRAM/compiler/router
T
History
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
..
tests
Supply router working except:
2018-09-18 12:57:39 -07:00
direction.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid_cell.py
Supply router working except:
2018-09-18 12:57:39 -07:00
grid_path.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
router.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
signal_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
signal_router.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
vector3d.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
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