mirror of https://github.com/VLSIDA/OpenRAM.git
106 lines
1.8 KiB
Verilog
106 lines
1.8 KiB
Verilog
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module sram_2_16_2_freepdk45_top (
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`ifdef USE_POWER_PINS
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vdd,
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gnd,
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`endif
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clk0,
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addr0,
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din0,
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csb0,
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web0,
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dout0
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);
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parameter DATA_WIDTH = 2;
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parameter ADDR_WIDTH= 4;
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parameter BANK_SEL = 1;
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parameter NUM_WMASK = 0;
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`ifdef USE_POWER_PINS
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inout vdd;
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inout gnd;
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`endif
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input clk0;
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input [ADDR_WIDTH - 1 : 0] addr0;
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input [DATA_WIDTH - 1: 0] din0;
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input csb0;
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input web0;
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output reg [DATA_WIDTH - 1 : 0] dout0;
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reg [BANK_SEL - 1 : 0] addr0_reg;
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wire [DATA_WIDTH - 1 : 0] dout0_bank0;
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reg web0_bank0;
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reg csb0_bank0;
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wire [DATA_WIDTH - 1 : 0] dout0_bank1;
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reg web0_bank1;
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reg csb0_bank1;
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sram_2_16_2_freepdk45 bank0 (
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`ifdef USE_POWER_PINS
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.vdd(vdd),
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.gnd(gnd),
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`endif
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.clk0(clk0),
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.addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din0(din0),
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.csb0(csb0_bank0),
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.web0(web0_bank0),
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.dout0(dout0_bank0)
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);
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sram_2_16_2_freepdk45 bank1 (
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`ifdef USE_POWER_PINS
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.vdd(vdd),
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.gnd(gnd),
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`endif
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.clk0(clk0),
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.addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
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.din0(din0),
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.csb0(csb0_bank1),
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.web0(web0_bank1),
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.dout0(dout0_bank1)
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);
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always @(posedge clk0) begin
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addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
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end
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always @(*) begin
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case (addr0_reg)
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0: begin
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dout0 = dout0_bank0;
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end
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1: begin
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dout0 = dout0_bank1;
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end
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endcase
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end
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always @(*) begin
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csb0_bank0 = 1'b1;
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web0_bank0 = 1'b1;
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csb0_bank1 = 1'b1;
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web0_bank1 = 1'b1;
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case (addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
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0: begin
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web0_bank0 = web0;
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csb0_bank0 = csb0;
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end
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1: begin
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web0_bank1 = web0;
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csb0_bank1 = csb0;
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end
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endcase
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end
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endmodule
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