mirror of https://github.com/VLSIDA/OpenRAM.git
72 lines
2.0 KiB
Python
72 lines
2.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from .drc_value import *
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from .drc_lut import *
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class design_rules(dict):
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"""
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This is a class that implements the design rules structures.
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"""
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def __init__(self, name):
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self.tech_name = name
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self.rules = {}
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def add(self, name, value):
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self.rules[name] = value
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def __call__(self, name, *args):
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rule = self.rules[name]
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if callable(rule):
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return rule(*args)
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else:
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return rule
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def __setitem__(self, b, c):
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"""
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For backward compatibility with existing rules.
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"""
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self.rules[b] = c
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def __contains__(self, b):
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"""
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Allows checking existence of rules
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"""
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return b in self.rules
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def __getitem__(self, b):
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"""
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For backward compatibility with existing rules.
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"""
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rule = self.rules[b]
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if not callable(rule):
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return rule
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else:
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debug.error("Must call complex DRC rule {} with arguments.".format(b),-1)
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def keys(self):
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return self.rules.keys()
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def add_layer(self, name, width, spacing, area=0):
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# Minimum width
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self.add("minwidth_{}".format(name), width)
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# Minimum spacing (could be a table too)
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self.add("{0}_to_{0}".format(name), spacing)
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# Minimum area
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self.add("minarea_{}".format(name), area)
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def add_enclosure(self, name, layer, enclosure, extension=None):
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self.add("{0}_enclose_{1}".format(name, layer), enclosure)
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# Reserved for asymmetric enclosures
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if extension:
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self.add("{0}_extend_{1}".format(name, layer), extension)
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else:
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self.add("{0}_extend_{1}".format(name, layer), enclosure)
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