mirror of https://github.com/VLSIDA/OpenRAM.git
27 lines
970 B
Python
27 lines
970 B
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.tech import cell_properties as props
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from .bitcell_base import bitcell_base
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class dummy_bitcell_2port(bitcell_base):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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def __init__(self, name):
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super().__init__(name, prop=props.bitcell_2port)
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debug.info(2, "Create dummy bitcell 2 port object")
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def build_graph(self, graph, inst_name, port_nets):
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""" Adds edges based on inputs/outputs. Overrides base class function. """
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pass
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