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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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8eb4812e166571db8892ac64652fc5bc7a3fa985
OpenRAM/technology/freepdk45/sp_lib
T
History
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
..
cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
replica_cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_6t.sp
Modify replica cell spice in FreePDK45 to short Qbar to vdd
2018-11-05 11:42:42 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
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