mirror of https://github.com/VLSIDA/OpenRAM.git
550 lines
24 KiB
Python
550 lines
24 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import math
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import tech
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from globals import OPTS
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from sram_factory import factory
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import graph_util
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class simulation():
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = self.sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.write_size = self.sram.write_size
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self.num_spare_rows = self.sram.num_spare_rows
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if not self.sram.num_spare_cols:
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self.num_spare_cols = 0
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else:
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self.num_spare_cols = self.sram.num_spare_cols
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self.sp_file = spfile
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self.all_ports = self.sram.all_ports
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self.readwrite_ports = self.sram.readwrite_ports
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self.read_ports = self.sram.read_ports
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self.write_ports = self.sram.write_ports
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self.words_per_row = self.sram.words_per_row
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if self.write_size:
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self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
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else:
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self.num_wmasks = 0
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def set_corner(self, corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_spice_constants(self):
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"] * 2
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self.load = tech.spice["dff_in_cap"] * 4
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self.v_high = self.vdd_voltage - tech.spice["nom_threshold"]
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self.v_low = tech.spice["nom_threshold"]
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self.gnd_voltage = 0
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def create_signal_names(self):
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self.addr_name = "a"
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self.din_name = "din"
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self.dout_name = "dout"
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self.pins = self.gen_pin_names(port_signal_names=(self.addr_name, self.din_name, self.dout_name),
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port_info=(len(self.all_ports), self.write_ports, self.read_ports),
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abits=self.addr_size,
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dbits=self.word_size + self.num_spare_cols)
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debug.check(len(self.sram.pins) == len(self.pins),
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"Number of pins generated for characterization \
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do not match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins,
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self.pins))
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def set_stimulus_variables(self):
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# Clock signals
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self.cycle_times = []
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self.t_current = 0
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# control signals: only one cs_b for entire multiported sram, one we_b for each write port
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self.csb_values = {port: [] for port in self.all_ports}
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self.web_values = {port: [] for port in self.readwrite_ports}
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# Raw values added as a bit vector
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self.addr_value = {port: [] for port in self.all_ports}
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self.data_value = {port: [] for port in self.write_ports}
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self.wmask_value = {port: [] for port in self.write_ports}
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self.spare_wen_value = {port: [] for port in self.write_ports}
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# Three dimensional list to handle each addr and data bits for each port over the number of checks
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self.addr_values = {port: [[] for bit in range(self.addr_size)] for port in self.all_ports}
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self.data_values = {port: [[] for bit in range(self.word_size + self.num_spare_cols)] for port in self.write_ports}
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self.wmask_values = {port: [[] for bit in range(self.num_wmasks)] for port in self.write_ports}
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self.spare_wen_values = {port: [[] for bit in range(self.num_spare_cols)] for port in self.write_ports}
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# For generating comments in SPICE stimulus
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self.cycle_comments = []
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self.fn_cycle_comments = []
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def add_control_one_port(self, port, op):
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"""Appends control signals for operation to a given port"""
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# Determine values to write to port
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web_val = 1
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csb_val = 1
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if op == "read":
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csb_val = 0
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elif op == "write":
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csb_val = 0
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web_val = 0
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elif op != "noop":
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debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port, op), 1)
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# Append the values depending on the type of port
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self.csb_values[port].append(csb_val)
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# If port is in both lists, add rw control signal. Condition indicates its a RW port.
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if port in self.readwrite_ports:
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self.web_values[port].append(web_val)
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def add_data(self, data, port):
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""" Add the array of data values """
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debug.check(len(data)==(self.word_size + self.num_spare_cols), "Invalid data word size.")
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self.data_value[port].append(data)
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bit = self.word_size + self.num_spare_cols - 1
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for c in data:
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if c=="0":
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self.data_values[port][bit].append(0)
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elif c=="1":
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self.data_values[port][bit].append(1)
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else:
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debug.error("Non-binary data string", 1)
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bit -= 1
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def add_address(self, address, port):
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""" Add the array of address values """
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debug.check(len(address)==self.addr_size, "Invalid address size.")
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self.addr_value[port].append(address)
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bit = self.addr_size - 1
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for c in address:
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if c=="0":
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self.addr_values[port][bit].append(0)
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elif c=="1":
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self.addr_values[port][bit].append(1)
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else:
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debug.error("Non-binary address string", 1)
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bit -= 1
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def add_wmask(self, wmask, port):
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""" Add the array of address values """
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debug.check(len(wmask) == self.num_wmasks, "Invalid wmask size.")
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self.wmask_value[port].append(wmask)
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bit = self.num_wmasks - 1
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for c in wmask:
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if c == "0":
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self.wmask_values[port][bit].append(0)
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elif c == "1":
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self.wmask_values[port][bit].append(1)
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else:
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debug.error("Non-binary wmask string", 1)
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bit -= 1
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def add_spare_wen(self, spare_wen, port):
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""" Add the array of spare write enable values (for spare cols) """
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debug.check(len(spare_wen) == self.num_spare_cols, "Invalid spare enable size.")
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self.spare_wen_value[port].append(spare_wen)
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bit = self.num_spare_cols - 1
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for c in spare_wen:
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if c == "0":
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self.spare_wen_values[port][bit].append(0)
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elif c == "1":
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self.spare_wen_values[port][bit].append(1)
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else:
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debug.error("Non-binary spare enable signal string", 1)
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bit -= 1
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def add_write(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle. """
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debug.check(port in self.write_ports,
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"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
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self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "write")
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self.add_data(data, port)
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self.add_address(address, port)
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self.add_wmask(wmask, port)
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self.add_spare_wen("1" * self.num_spare_cols, port)
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(unselected_port)
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def add_read(self, comment, address, port):
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""" Add the control values for a read cycle. """
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debug.check(port in self.read_ports,
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"Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port,
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self.read_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "read")
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self.add_address(address, port)
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# If the port is also a readwrite then add
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# the same value as previous cycle
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if port in self.write_ports:
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try:
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self.add_data(self.data_value[port][-1], port)
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except:
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self.add_data("0" * (self.word_size + self.num_spare_cols), port)
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try:
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self.add_wmask(self.wmask_value[port][-1], port)
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except:
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self.add_wmask("0" * self.num_wmasks, port)
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self.add_spare_wen("0" * self.num_spare_cols, port)
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(unselected_port)
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def add_noop_all_ports(self, comment):
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""" Add the control values for a noop to all ports. """
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.append_cycle_comment("All", comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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for port in self.all_ports:
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self.add_noop_one_port(port)
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def add_write_one_port(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle. Does not increment the period. """
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debug.check(port in self.write_ports,
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"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
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self.write_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "write")
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self.add_data(data, port)
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self.add_address(address, port)
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self.add_wmask(wmask, port)
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self.add_spare_wen("1" * self.num_spare_cols, port)
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def add_read_one_port(self, comment, address, port):
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""" Add the control values for a read cycle. Does not increment the period. """
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debug.check(port in self.read_ports,
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"Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port,
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self.read_ports))
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debug.info(2, comment)
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self.fn_cycle_comments.append(comment)
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self.add_control_one_port(port, "read")
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self.add_address(address, port)
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# If the port is also a readwrite then add
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# the same value as previous cycle
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if port in self.write_ports:
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try:
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self.add_data(self.data_value[port][-1], port)
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except:
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self.add_data("0" * (self.word_size + self.num_spare_cols), port)
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try:
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self.add_wmask(self.wmask_value[port][-1], port)
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except:
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self.add_wmask("0" * self.num_wmasks, port)
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self.add_spare_wen("0" * self.num_spare_cols, port)
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def add_noop_one_port(self, port):
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""" Add the control values for a noop to a single port. Does not increment the period. """
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self.add_control_one_port(port, "noop")
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try:
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self.add_address(self.addr_value[port][-1], port)
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except:
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self.add_address("0" * self.addr_size, port)
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# If the port is also a readwrite then add
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# the same value as previous cycle
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if port in self.write_ports:
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try:
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self.add_data(self.data_value[port][-1], port)
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except:
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self.add_data("0" * (self.word_size + self.num_spare_cols), port)
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try:
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self.add_wmask(self.wmask_value[port][-1], port)
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except:
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self.add_wmask("0" * self.num_wmasks, port)
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self.add_spare_wen("0" * self.num_spare_cols, port)
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def add_noop_clock_one_port(self, port):
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""" Add the control values for a noop to a single port. Increments the period. """
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debug.info(2, 'Clock only on port {}'.format(port))
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self.fn_cycle_comments.append('Clock only on port {}'.format(port))
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self.append_cycle_comment(port, 'Clock only on port {}'.format(port))
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_noop_one_port(port)
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(unselected_port)
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def append_cycle_comment(self, port, comment):
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"""Add comment to list to be printed in stimulus file"""
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#Clean up time before appending. Make spacing dynamic as well.
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time = "{0:.2f} ns:".format(self.t_current)
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time_spacing = len(time) + 6
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self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
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port,
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time,
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time_spacing,
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comment))
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def gen_cycle_comment(self, op, word, addr, wmask, port, t_current):
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if op == "noop":
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str = "\tIdle during cycle {0} ({1}ns - {2}ns)"
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comment = str.format(int(t_current / self.period),
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t_current,
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t_current + self.period)
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elif op == "write":
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "partial_write":
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str = "\tWriting (partial) {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)"
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comment = str.format(word,
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addr,
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wmask,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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else:
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str = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)"
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comment = str.format(word,
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addr,
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port,
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int(t_current / self.period),
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t_current,
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t_current + self.period)
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return comment
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def gen_pin_names(self, port_signal_names, port_info, abits, dbits):
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"""Creates the pins names of the SRAM based on the no. of ports."""
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# This may seem redundant as the pin names are already defined in the sram. However, it is difficult
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# to extract the functionality from the names, so they are recreated. As the order is static, changing
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# the order of the pin names will cause issues here.
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pin_names = []
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(addr_name, din_name, dout_name) = port_signal_names
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(total_ports, write_index, read_index) = port_info
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for write_input in write_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(din_name, write_input, i))
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for port in range(total_ports):
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for i in range(abits):
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pin_names.append("{0}{1}_{2}".format(addr_name, port, i))
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#Control signals not finalized.
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for port in range(total_ports):
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pin_names.append("CSB{0}".format(port))
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for port in range(total_ports):
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format("clk", port))
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if self.write_size:
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for port in write_index:
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for bit in range(self.num_wmasks):
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pin_names.append("WMASK{0}_{1}".format(port, bit))
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if self.num_spare_cols:
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for port in write_index:
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for bit in range(self.num_spare_cols):
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pin_names.append("SPARE_WEN{0}_{1}".format(port, bit))
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for read_output in read_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name, read_output, i))
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pin_names.append("{0}".format("vdd"))
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pin_names.append("{0}".format("gnd"))
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return pin_names
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def get_column_addr(self):
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"""Returns column address of probe bit"""
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return self.probe_address[:self.sram.col_addr_size]
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def add_graph_exclusions(self):
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"""
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Exclude portions of SRAM from timing graph which are not relevant
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"""
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# other initializations can only be done during analysis when a bit has been selected
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# for testing.
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self.sram.bank.graph_exclude_precharge()
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self.sram.graph_exclude_addr_dff()
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self.sram.graph_exclude_data_dff()
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self.sram.graph_exclude_ctrl_dffs()
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self.sram.bank.bitcell_array.graph_exclude_replica_col_bits()
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def set_internal_spice_names(self):
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"""
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Sets important names for characterization such as Sense amp enable and internal bit nets.
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"""
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port = self.read_ports[0]
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if not OPTS.use_pex:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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sen_with_port = self.get_sen_name(self.graph.all_paths)
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if sen_with_port.endswith(str(port)):
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self.sen_name = sen_with_port[:-len(str(port))]
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else:
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self.sen_name = sen_with_port
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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debug.info(2, "s_en name = {}".format(self.sen_name))
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column_addr = self.get_column_addr()
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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port_pos = -1 - len(str(column_addr)) - len(str(port))
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if bl_name_port.endswith(str(port) + "_" + str(column_addr)):
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self.bl_name = bl_name_port[:port_pos] + "{}" + bl_name_port[port_pos + len(str(port)):]
|
|
elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
|
|
self.bl_name = bl_name_port
|
|
else:
|
|
self.bl_name = bl_name_port
|
|
debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
|
|
|
|
if br_name_port.endswith(str(port) + "_" + str(column_addr)):
|
|
self.br_name = br_name_port[:port_pos] + "{}" + br_name_port[port_pos + len(str(port)):]
|
|
elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
|
|
self.br_name = br_name_port
|
|
else:
|
|
self.br_name = br_name_port
|
|
debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
|
|
debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name))
|
|
else:
|
|
self.graph.get_all_paths('{}{}'.format("clk", port),
|
|
'{}{}_{}'.format(self.dout_name, port, self.probe_data))
|
|
|
|
self.sen_name = self.get_sen_name(self.graph.all_paths)
|
|
debug.info(2, "s_en name = {}".format(self.sen_name))
|
|
|
|
self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size - 1)
|
|
self.br_name = "br{0}_{1}".format(port, OPTS.word_size - 1)
|
|
debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name))
|
|
|
|
def get_sen_name(self, paths, assumed_port=None):
|
|
"""
|
|
Gets the signal name associated with the sense amp enable from input paths.
|
|
Only expects a single path to contain the sen signal name.
|
|
"""
|
|
|
|
sa_mods = factory.get_mods(OPTS.sense_amp)
|
|
# Any sense amp instantiated should be identical, any change to that
|
|
# will require some identification to determine the mod desired.
|
|
debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.")
|
|
enable_name = sa_mods[0].get_enable_name()
|
|
sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
|
|
if OPTS.use_pex:
|
|
sen_name = sen_name.split('.')[-1]
|
|
return sen_name
|
|
|
|
def create_graph(self):
|
|
"""
|
|
Creates timing graph to generate the timing paths for the SRAM output.
|
|
"""
|
|
|
|
self.sram.clear_exclude_bits() # Removes previous bit exclusions
|
|
self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column)
|
|
|
|
# Generate new graph every analysis as edges might change depending on test bit
|
|
self.graph = graph_util.timing_graph()
|
|
self.sram_instance_name = "X{}".format(self.sram.name)
|
|
self.sram.build_graph(self.graph, self.sram_instance_name, self.pins)
|
|
|
|
def get_bl_name_search_exclusions(self):
|
|
"""
|
|
Gets the mods as a set which should be excluded while searching for name.
|
|
"""
|
|
|
|
# Exclude the RBL as it contains bitcells which are not in the main bitcell array
|
|
# so it makes the search awkward
|
|
return set(factory.get_mods(OPTS.replica_bitline))
|
|
|
|
def get_alias_in_path(self, paths, internal_net, mod, exclusion_set=None):
|
|
"""
|
|
Finds a single alias for the internal_net in given paths.
|
|
More or less hits cause an error
|
|
"""
|
|
net_found = False
|
|
for path in paths:
|
|
aliases = self.sram.find_aliases(self.sram_instance_name, self.pins, path, internal_net, mod, exclusion_set)
|
|
if net_found and len(aliases) >= 1:
|
|
debug.error('Found multiple paths with {} net.'.format(internal_net), 1)
|
|
elif len(aliases) > 1:
|
|
debug.error('Found multiple {} nets in single path.'.format(internal_net), 1)
|
|
elif not net_found and len(aliases) == 1:
|
|
path_net_name = aliases[0]
|
|
net_found = True
|
|
if not net_found:
|
|
debug.error("Could not find {} net in timing paths.".format(internal_net), 1)
|
|
|
|
return path_net_name
|
|
|
|
def get_bl_name(self, paths, port):
|
|
"""
|
|
Gets the signal name associated with the bitlines in the bank.
|
|
"""
|
|
cell_mod = factory.create(module_type=OPTS.bitcell)
|
|
cell_bl = cell_mod.get_bl_name(port)
|
|
cell_br = cell_mod.get_br_name(port)
|
|
|
|
bl_names = []
|
|
exclude_set = self.get_bl_name_search_exclusions()
|
|
for int_net in [cell_bl, cell_br]:
|
|
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
|
|
if OPTS.use_pex:
|
|
for i in range(len(bl_names)):
|
|
bl_names[i] = bl_names[i].split('.')[-1]
|
|
return bl_names[0], bl_names[1]
|
|
|
|
|
|
|