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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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8ca9ba4244dded694966a9bbb3554001c1e50097
OpenRAM/compiler/base
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Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
..
contact.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
design.py
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
2018-02-26 16:32:28 -08:00
geometry.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
hierarchy_layout.py
Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
hierarchy_spice.py
Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev
2018-03-02 10:30:16 -08:00
lef.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
route.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
utils.py
Move utils to base.
2018-02-09 10:42:23 -08:00
vector.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
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