mirror of https://github.com/VLSIDA/OpenRAM.git
303 lines
10 KiB
Python
303 lines
10 KiB
Python
# See LICENSE for licensing information.
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#
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#Copyright (c) 2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import design
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from tech import parameter
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import debug
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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class pwrite_driver(design.design):
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"""
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The pwrite_driver is two tristate inverters that drive the bitlines.
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The data input is first inverted before one tristate.
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The inverted enable is also generated to control one tristate.
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"""
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def __init__(self, name, size=0):
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debug.error("pwrite_driver not implemented yet.", -1)
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debug.info(1, "creating pwrite_driver {}".format(name))
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super().__init__(name)
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self.size = size
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self.beta = parameter["beta"]
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self.pmos_width = self.beta*self.size*parameter["min_tx_size"]
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self.nmos_width = self.size*parameter["min_tx_size"]
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# The tech M2 pitch is based on old via orientations
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self.m2_pitch = self.m2_space + self.m2_width
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# Width is matched to the bitcell,
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# Height will be variable
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self.bitcell = factory.create(module_type="bitcell")
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self.width = self.bitcell.width
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# Creates the netlist and layout
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# Since it has variable height, it is not a pgate.
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.DRC_LVS()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_insts()
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def create_layout(self):
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self.place_modules()
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self.route_wires()
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self.route_supplies()
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self.add_boundary()
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def add_pins(self):
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self.add_pin("din", "INPUT")
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self.add_pin("bl", "OUTPUT")
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self.add_pin("br", "OUTPUT")
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self.add_pin("en", "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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# Tristate inverter
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self.tri = factory.create(module_type="ptristate_inv", height="min")
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self.add_mod(self.tri)
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debug.check(self.tri.width<self.width,
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"Could not create tristate inverter to match bitcell width")
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#self.tbuf = factory.create(module_type="ptristate_buf",
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#height="min")
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#self.add_mod(self.tbuf)
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#debug.check(self.tbuf.width<self.width,
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#"Could not create tristate buffer to match bitcell width")
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# Inverter for din and en
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self.inv = factory.create(module_type="pinv", under_rail_vias=True)
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self.add_mod(self.inv)
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def create_insts(self):
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# Enable inverter
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self.en_inst = self.add_inst(name="en_inv", mod=self.inv)
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self.connect_inst(["en", "en_bar", "vdd", "gnd"])
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# Din inverter
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self.din_inst = self.add_inst(name="din_inv", mod=self.inv)
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self.connect_inst(["din", "din_bar", "vdd", "gnd"])
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# Bitline tristate
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self.bl_inst = self.add_inst(name="bl_tri", mod=self.tri)
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self.connect_inst(["din_bar", "bl", "en", "en_bar", "vdd", "gnd"])
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# Bitline bar tristate
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self.br_inst = self.add_inst(name="br_tri", mod=self.tri)
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self.connect_inst(["din", "br", "en", "en_bar", "vdd", "gnd"])
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def place_modules(self):
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# Add enable to the right
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self.din_inst.place(vector(0, 0))
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# Add BR tristate above
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self.br_inst.place(vector(0, self.en_inst.uy()+self.br_inst.height), mirror="MX")
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# Add BL tristate buffer
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#print(self.bl_inst.width,self.width)
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self.bl_inst.place(vector(self.width,self.br_inst.uy()), mirror="MY")
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# Add din to the left
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self.en_inst.place(vector(self.width, self.bl_inst.uy()+self.en_inst.height), rotate=180)
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self.height = self.en_inst.uy()
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def route_bitlines(self):
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"""
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Route the bitlines to the spacing of the bitcell
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( even though there may be a column mux )
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"""
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# Second from left track and second from right track
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right_x = self.width + self.m2_pitch
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left_x = -self.m2_pitch
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bl_xoffset = left_x
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bl_out=vector(bl_xoffset, self.height)
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bl_in=self.bl_inst.get_pin("out").center()
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self.add_via_center(layers=self.m1_stack,
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offset=bl_in)
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bl_mid = vector(bl_out.x,bl_in.y)
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self.add_path("m2", [bl_in, bl_mid, bl_out])
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self.add_layout_pin_rect_center(text="bl",
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layer="m2",
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offset=bl_out)
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br_xoffset = right_x
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br_out=vector(br_xoffset, self.height)
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br_in=self.br_inst.get_pin("out").center()
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self.add_via_center(layers=self.m1_stack,
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offset=br_in)
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br_mid = vector(br_out.x,br_in.y)
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self.add_path("m2", [br_in, br_mid, br_out])
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self.add_layout_pin_rect_center(text="br",
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layer="m2",
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offset=br_out)
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#br_xoffset = b.get_pin("br".cx()
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#self.br_inst.get_pin("br")
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def route_din(self):
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# Left
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track_xoff = self.get_m2_track(1)
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din_loc = self.din_inst.get_pin("A").center()
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self.add_via_stack_center("m1", "m2", din_loc)
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din_track = vector(track_xoff,din_loc.y)
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br_in = self.br_inst.get_pin("in").center()
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self.add_via_stack_center("m1", "m2", br_in)
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br_track = vector(track_xoff,br_in.y)
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din_in = vector(track_xoff,0)
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self.add_path("m2", [din_in, din_track, din_loc, din_track, br_track, br_in])
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self.add_layout_pin_rect_center(text="din",
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layer="m2",
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offset=din_in)
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def route_din_bar(self):
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# Left
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track_xoff = self.get_m4_track(self.din_bar_track)
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din_bar_in = self.din_inst.get_pin("Z").center()
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self.add_via_stack_center("m1", "m3", din_bar_in)
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din_bar_track = vector(track_xoff,din_bar_in.y)
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bl_in = self.bl_inst.get_pin("in").center()
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self.add_via_stack_center("m1", "m3", bl_in)
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bl_track = vector(track_xoff,bl_in.y)
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din_in = vector(track_xoff,0)
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self.add_wire(self.m3_stack, [din_bar_in, din_bar_track, bl_track, bl_in])
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self.add_layout_pin_rect_center(text="din",
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layer="m4",
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offset=din_in)
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def route_en_bar(self):
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# Enable in track
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track_xoff = self.get_m4_track(self.en_bar_track)
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# This M2 pitch is a hack since the A and Z pins align horizontally
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en_bar_loc = self.en_inst.get_pin("Z").uc()
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en_bar_track = vector(track_xoff, en_bar_loc.y)
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self.add_via_stack_center("m1", "m3", en_bar_loc)
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# This is a U route to the right down then left
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bl_en_loc = self.bl_inst.get_pin("en_bar").center()
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bl_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack_center("m1", "m3", bl_en_loc)
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br_en_loc = self.br_inst.get_pin("en_bar").center()
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br_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack_center("m1", "m3", br_en_loc)
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# L shape
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self.add_wire(self.m3_stack,
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[en_bar_loc, en_bar_track, bl_en_track])
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# U shape
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self.add_wire(self.m3_stack,
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[bl_en_loc, bl_en_track, br_en_track, br_en_loc])
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def route_en(self):
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# Enable in track
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track_xoff = self.get_m4_track(self.en_track)
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# The en pin will be over the vdd rail
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vdd_yloc = self.en_inst.get_pin("vdd").cy()
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self.add_layout_pin_segment_center(text="en",
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layer="m3",
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start=vector(0,vdd_yloc),
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end=vector(self.width,vdd_yloc))
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en_loc = self.en_inst.get_pin("A").center()
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en_rail = vector(en_loc.x, vdd_yloc)
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self.add_via_stack_center("m1", "m2", en_loc)
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self.add_path("m2", [en_loc, en_rail])
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self.add_via_stack_center("m2", "m3", en_rail)
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# Start point in the track on the pin rail
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en_track = vector(track_xoff, vdd_yloc)
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self.add_via_stack_center("m3", "m4", en_track)
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# This is a U route to the right down then left
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bl_en_loc = self.bl_inst.get_pin("en").center()
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bl_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack_center("m1", "m3", bl_en_loc)
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br_en_loc = self.br_inst.get_pin("en").center()
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br_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack_center("m1", "m3", br_en_loc)
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# U shape
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self.add_wire(self.m3_stack,
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[en_track, bl_en_track, bl_en_loc, bl_en_track, br_en_track, br_en_loc])
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def get_m4_track(self,i):
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return 0.5*self.m4_space + i*(self.m4_width+self.m4_space)
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def get_m3_track(self,i):
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return 0.5*self.m3_space + i*(self.m3_width+self.m3_space)
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def get_m2_track(self,i):
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return 0.5*self.m2_space + i*(self.m2_width+self.m2_space)
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def route_wires(self):
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# M4 tracks
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self.din_bar_track = 2
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self.en_track = 0
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self.en_bar_track = 1
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self.route_bitlines()
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self.route_din()
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self.route_din_bar()
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self.route_en()
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self.route_en_bar()
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def route_supplies(self):
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for inst in [self.en_inst, self.din_inst, self.bl_inst, self.br_inst]:
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# Continous vdd rail along with label.
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vdd_pin=inst.get_pin("vdd")
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self.add_layout_pin(text="vdd",
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layer="m1",
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offset=vdd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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# Continous gnd rail along with label.
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gnd_pin=inst.get_pin("gnd")
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self.add_layout_pin(text="gnd",
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layer="m1",
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offset=gnd_pin.ll().scale(0,1),
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width=self.width,
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height=vdd_pin.height())
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def get_w_en_cin(self):
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"""Get the relative capacitance of a single input"""
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# This is approximated from SCMOS. It has roughly 5 3x transistor gates.
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return 5*3
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