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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-09-07 11:21:14 +02:00
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8b6a28b6fd6cf0153b7bbc6ab0519119dbf375f9
OpenRAM
/
technology
/
scn4m_subm
/
sp_lib
T
History
Hunter Nichols
8b6a28b6fd
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
..
cell_1rw_1r.sp
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.sp
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
replica_cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
