mirror of https://github.com/VLSIDA/OpenRAM.git
102 lines
3.6 KiB
Python
102 lines
3.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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from .bitcell_base import bitcell_base
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class bitcell_2port(bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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def __init__(self, name):
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super().__init__(name, prop=props.bitcell_2port)
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debug.info(2, "Create bitcell with 2 ports")
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self.bl_names = ["bl0", "bl1"]
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self.br_names = ["br0", "br1"]
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self.wl_names = ["wl0", "wl1"]
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def get_bitcell_pins(self, col, row):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = ["bl0_{0}".format(col),
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"br0_{0}".format(col),
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"bl1_{0}".format(col),
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"br1_{0}".format(col),
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"wl0_{0}".format(row),
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"wl1_{0}".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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return self.wl_names
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def get_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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return ["bl0", "br0", "bl1", "br1"]
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def get_all_bl_names(self):
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""" Creates a list of all bl pins names """
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return ["bl0", "bl1"]
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def get_all_br_names(self):
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""" Creates a list of all br pins names """
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return ["br0", "br1"]
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def get_read_bl_names(self):
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""" Creates a list of bl pin names associated with read ports """
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return ["bl0", "bl1"]
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def get_read_br_names(self):
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""" Creates a list of br pin names associated with read ports """
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return ["br0", "br1"]
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def get_write_bl_names(self):
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""" Creates a list of bl pin names associated with write ports """
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return ["bl0"]
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def get_write_br_names(self):
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""" Creates a list of br pin names asscociated with write ports"""
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return ["br1"]
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def get_bl_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_2port only.")
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return self.bl_names[port]
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def get_br_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_2port only.")
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return self.br_names[port]
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def get_wl_name(self, port=0):
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"""Get wl name by port"""
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debug.check(port < 2, "Two ports for bitcell_2port only.")
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return self.wl_names[port]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.get_original_pin_names(), port_nets)}
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)
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# Port 1 edges
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graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
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graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
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