Jesse Cirimelli-Low 8a4b34dee1 proper tiling

2023-07-26 18:05:36 -07:00

..

__init__.py

Verilog ROM model created for testing

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channel_route.py

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contact.py

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delay_data.py

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design.py

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errors.py

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geometry.py

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hierarchy_design.py

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hierarchy_layout.py

proper tiling

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hierarchy_spice.py

fix typo bug in spice comments code

2023-07-10 13:21:24 -07:00

lef.py

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logical_effort.py

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pin_layout.py

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power_data.py

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rom_verilog.py

Fixed formatting on all files

2023-06-14 12:28:36 -07:00

route.py

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timing_graph.py

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utils.py

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vector3d.py

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vector.py

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verilog.py

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wire_path.py

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wire_spice_model.py

add fixme note for unit conversion

2023-06-28 14:05:42 -07:00

wire.py

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