mirror of https://github.com/VLSIDA/OpenRAM.git
112 lines
4.8 KiB
Python
112 lines
4.8 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram.base import geometry
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from openram.sram_factory import factory
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from openram.modules.row_cap_array import row_cap_array
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from openram.modules.pattern import pattern
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from math import ceil
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class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
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super().__init__(rows, cols, column_offset=column_offset, location=location, name=name)
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self.mirror = mirror
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self.location = location
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def add_modules(self):
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""" Add the modules used in this design """
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if self.location == "left":
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self.top_corner = factory.create(module_type="corner", location="ul")
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self.bottom_corner =factory.create(module_type="corner", location="ll")
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#self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
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#self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
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else:
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self.top_corner = factory.create(module_type="corner", location="ur")
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self.bottom_corner = factory.create(module_type="corner", location="lr")
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#self.rowend1 = factory.create(module_type="row_cap", version="rowend")
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#self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
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self.rowend = factory.create(module_type="row_cap", version="rowend")
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self.rowenda = factory.create(module_type="row_cap", version="rowenda")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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self.all_inst={}
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self.cell_inst={}
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bit_block = []
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if self.location == "left":
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top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="MY")
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bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="XY")
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rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="XY")
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rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="MY")
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elif self.location == "right":
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top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False)
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bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="MX")
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rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="MX")
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rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True)
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pattern.append_row_to_block(bit_block, [bottom_corner])
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for row in range(1,self.row_size-1):
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if row % 2 == 0:
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pattern.append_row_to_block(bit_block, [rowend])
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else:
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pattern.append_row_to_block(bit_block, [rowenda])
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pattern.append_row_to_block(bit_block, [top_corner])
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self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
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self.pattern.connect_array_raw()
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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return bitcell_pins
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def get_strap_pins(self, row, col):
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strap_pins = []
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strap_pins.append("vdd") # vdd
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strap_pins.append("vdd") # vpb
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strap_pins.append("gnd") # vnb
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return strap_pins
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def create_all_wordline_names(self, row_size=None, start_row=0):
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if row_size == None:
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row_size = self.row_size
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row_size = row_size - 2
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for row in range(start_row, row_size):
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for port in self.all_ports:
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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