mirror of https://github.com/VLSIDA/OpenRAM.git
51 lines
1.1 KiB
Python
Executable File
51 lines
1.1 KiB
Python
Executable File
#!/usr/bin/env python2.7
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"""
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SRAM Compiler
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The output files append the given suffixes to the output name:
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a spice (.sp) file for circuit simulation
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a GDS2 (.gds) file containing the layout
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a LEF (.lef) file for preliminary P&R (real one should be from layout)
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a Liberty (.lib) file for timing analysis/optimization
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"""
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import sys,os
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import datetime
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import re
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import importlib
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from globals import *
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(OPTS, args) = parse_args(is_unit_test=False)
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# These depend on arguments, so don't load them until now.
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import debug
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# Only print banner here so it's not in unit tests
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print_banner()
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init_openram(args[0])
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# Start importing design modules after we have the config file
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import verify
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import sram
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# Keep track of running stats
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start_time = datetime.datetime.now()
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print_time("Start",start_time)
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# import SRAM test generation
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s = sram.sram(word_size=OPTS.word_size,
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num_words=OPTS.num_words,
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num_banks=OPTS.num_banks,
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name=OPTS.output_name)
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# Output the files for the resulting SRAM
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s.save_output()
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# Delete temp files etc.
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end_openram()
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print_time("End",datetime.datetime.now(), start_time)
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