mirror of https://github.com/VLSIDA/OpenRAM.git
244 lines
11 KiB
Python
244 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import hierarchy_layout
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import hierarchy_spice
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import globals
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import verify
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import debug
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import os
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from globals import OPTS
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import graph_util
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total_drc_errors = 0
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total_lvs_errors = 0
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class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
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"""
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Design Class for all modules to inherit the base features.
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Class consisting of a set of modules and instances of these modules
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"""
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name_map = []
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def __init__(self, name):
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self.gds_file = OPTS.openram_tech + "gds_lib/" + name + ".gds"
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self.sp_file = OPTS.openram_tech + "sp_lib/" + name + ".sp"
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self.name = name
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hierarchy_spice.spice.__init__(self, name)
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hierarchy_layout.layout.__init__(self, name)
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self.init_graph_params()
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def get_layout_pins(self,inst):
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""" Return a map of pin locations of the instance offset """
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# find the instance
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for i in self.insts:
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if i.name == inst.name:
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break
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else:
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debug.error("Couldn't find instance {0}".format(inst_name),-1)
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inst_map = inst.mod.pin_map
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return inst_map
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def DRC_LVS(self, final_verification=False, top_level=False):
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"""Checks both DRC and LVS for a module"""
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# Final verification option does not allow nets to be connected by label.
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# Unit tests will check themselves.
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if OPTS.is_unit_test:
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return
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if not OPTS.check_lvsdrc:
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return
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# Do not run if disabled in options.
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if (OPTS.inline_lvsdrc or top_level):
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global total_drc_errors
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global total_lvs_errors
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tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name)
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tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
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self.sp_write(tempspice)
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self.gds_write(tempgds)
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num_drc_errors = verify.run_drc(self.name, tempgds, final_verification)
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num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
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debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors))
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debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors))
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total_drc_errors += num_drc_errors
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total_lvs_errors += num_lvs_errors
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os.remove(tempspice)
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os.remove(tempgds)
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def DRC(self, final_verification=False):
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"""Checks DRC for a module"""
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# Unit tests will check themselves.
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# Do not run if disabled in options.
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if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
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global total_drc_errors
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tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
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self.gds_write(tempgds)
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num_errors = verify.run_drc(self.name, tempgds, final_verification)
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total_drc_errors += num_errors
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debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error))
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os.remove(tempgds)
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def LVS(self, final_verification=False):
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"""Checks LVS for a module"""
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# Unit tests will check themselves.
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# Do not run if disabled in options.
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if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
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global total_lvs_errors
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tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name)
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tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
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self.sp_write(tempspice)
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self.gds_write(tempgds)
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num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification)
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total_lvs_errors += num_errors
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debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors))
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os.remove(tempspice)
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os.remove(tempgds)
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def init_graph_params(self):
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"""Initializes parameters relevant to the graph creation"""
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#Only initializes a set for checking instances which should not be added
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self.graph_inst_exclude = set()
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def build_graph(self, graph, inst_name, port_nets):
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"""Recursively create graph from instances in module."""
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#Translate port names to external nets
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if len(port_nets) != len(self.pins):
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debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1)
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port_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
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debug.info(3, "Instance name={}".format(inst_name))
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for subinst, conns in zip(self.insts, self.conns):
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if subinst in self.graph_inst_exclude:
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continue
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subinst_name = inst_name+'.X'+subinst.name
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subinst_ports = self.translate_nets(conns, port_dict, inst_name)
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subinst.mod.build_graph(graph, subinst_name, subinst_ports)
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def build_names(self, name_dict, inst_name, port_nets):
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"""Collects all the nets and the parent inst of that net."""
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#Translate port names to external nets
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if len(port_nets) != len(self.pins):
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debug.error("Port length mismatch:\nExt nets={}, Ports={}".format(port_nets,self.pins),1)
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port_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
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debug.info(3, "Instance name={}".format(inst_name))
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for subinst, conns in zip(self.insts, self.conns):
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subinst_name = inst_name+'.X'+subinst.name
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subinst_ports = self.translate_nets(conns, port_dict, inst_name)
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for si_port, conn in zip(subinst_ports, conns):
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#Only add for first occurrence
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if si_port.lower() not in name_dict:
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mod_info = {'mod':self, 'int_net':conn}
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name_dict[si_port.lower()] = mod_info
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subinst.mod.build_names(name_dict, subinst_name, subinst_ports)
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def find_aliases(self, inst_name, port_nets, path_nets, alias, alias_mod, exclusion_set=None):
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"""Given a list of nets, will compare the internal alias of a mod to determine
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if the nets have a connection to this mod's net (but not inst).
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"""
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if exclusion_set == None:
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exclusion_set = set()
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try:
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self.name_dict
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except AttributeError:
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self.name_dict = {}
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self.build_names(self.name_dict, inst_name, port_nets)
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aliases = []
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for net in path_nets:
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net = net.lower()
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int_net = self.name_dict[net]['int_net']
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int_mod = self.name_dict[net]['mod']
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if int_mod.is_net_alias(int_net, alias, alias_mod, exclusion_set):
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aliases.append(net)
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return aliases
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def is_net_alias(self, known_net, net_alias, mod, exclusion_set):
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"""Checks if the alias_net in input mod is the same as the input net for this mod (self)."""
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if self in exclusion_set:
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return False
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#Check ports of this mod
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for pin in self.pins:
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if self.is_net_alias_name_check(known_net, pin, net_alias, mod):
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return True
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#Check connections of all other subinsts
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mod_set = set()
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for subinst, inst_conns in zip(self.insts, self.conns):
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for inst_conn, mod_pin in zip(inst_conns, subinst.mod.pins):
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if self.is_net_alias_name_check(known_net, inst_conn, net_alias, mod):
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return True
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elif inst_conn.lower() == known_net.lower() and subinst.mod not in mod_set:
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if subinst.mod.is_net_alias(mod_pin, net_alias, mod, exclusion_set):
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return True
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mod_set.add(subinst.mod)
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return False
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def is_net_alias_name_check(self, parent_net, child_net, alias_net, mod):
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"""Utility function for checking single net alias."""
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return self == mod and \
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child_net.lower() == alias_net.lower() and \
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parent_net.lower() == alias_net.lower()
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def get_mod_net(self, parent_net, child_inst, child_conns):
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"""Given an instance and net, returns the internal net in the mod
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corresponding to input net."""
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for conn, pin in zip(child_conns, child_inst.mod.pins):
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if parent_net.lower() == conn.lower():
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return pin
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return None
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def translate_nets(self, subinst_ports, port_dict, inst_name):
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"""Converts connection names to their spice hierarchy equivalent"""
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converted_conns = []
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for conn in subinst_ports:
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if conn in port_dict:
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converted_conns.append(port_dict[conn])
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else:
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converted_conns.append("{}.{}".format(inst_name, conn))
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return converted_conns
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def add_graph_edges(self, graph, port_nets):
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"""For every input, adds an edge to every output.
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Only intended to be used for gates and other simple modules."""
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#The final pin names will depend on the spice hierarchy, so
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#they are passed as an input.
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pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
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input_pins = self.get_inputs()
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output_pins = self.get_outputs()
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inout_pins = self.get_inouts()
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for inp in input_pins+inout_pins:
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for out in output_pins+inout_pins:
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if inp != out: #do not add self loops
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graph.add_edge(pin_dict[inp], pin_dict[out], self)
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def __str__(self):
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""" override print function output """
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pins = ",".join(self.pins)
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insts = [" {}".format(x) for x in self.insts]
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objs = [" {}".format(x) for x in self.objs]
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s = "********** design {0} **********".format(self.name)
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s += "\n pins ({0})={1}\n".format(len(self.pins), pins)
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s += "\n objs ({0})=\n{1}\n".format(len(self.objs), "\n".join(objs))
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s += "\n insts ({0})=\n{1}\n".format(len(self.insts), "\n".join(insts))
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return s
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def __repr__(self):
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""" override print function output """
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text="( design: " + self.name + " pins=" + str(self.pins) + " " + str(self.width) + "x" + str(self.height) + " )\n"
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for i in self.objs:
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text+=str(i)+",\n"
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for i in self.insts:
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text+=str(i)+",\n"
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return text
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