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luke
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OpenRAM
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852bfbc0315219e5d4938a9c55da7e6681fd9886
OpenRAM
/
compiler
/
bitcells
T
History
Hunter Nichols
98a00f985b
Changed the analytical delay model to accept multiport options. Little substance to the values generated.
2018-10-26 00:08:13 -07:00
..
bitcell_1rw_1r.py
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
bitcell.py
…
pbitcell.py
Changed the analytical delay model to accept multiport options. Little substance to the values generated.
2018-10-26 00:08:13 -07:00
replica_bitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00