mirror of https://github.com/VLSIDA/OpenRAM.git
46 lines
2.0 KiB
Python
46 lines
2.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer,drc,parameter
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class dummy_bitcell_1w_1r(design.design):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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(width,height) = utils.get_libcell_size("dummy_cell_1w_1r", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_1w_1r", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "dummy_cell_1w_1r")
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debug.info(2, "Create dummy bitcell 1w+1r object")
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self.width = dummy_bitcell_1w_1r.width
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self.height = dummy_bitcell_1w_1r.height
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self.pin_map = dummy_bitcell_1w_1r.pin_map
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self.add_pin_types(self.type_list)
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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#FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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def build_graph(self, graph, inst_name, port_nets):
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"""Dummy bitcells are cannot form a path and be part of the timing graph"""
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return
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