mirror of https://github.com/VLSIDA/OpenRAM.git
73 lines
2.6 KiB
Python
73 lines
2.6 KiB
Python
import sys,re,shutil
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import debug
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import tech
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import math
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .delay import delay
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class bitline_delay(delay):
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"""Functions to test for the worst case delay in a target SRAM
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The current worst case determines a feasible period for the SRAM then tests
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several bits and record the delay and differences between the bits.
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"""
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def __init__(self, sram, spfile, corner):
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delay.__init__(self,sram,spfile,corner)
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self.period = 1
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self.is_bitline_measure = True
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def create_measurement_names(self):
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"""Create measurement names. The names themselves currently define the type of measurement"""
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#Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
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self.bitline_meas_names = ["bl_volt", "br_volt"]
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def write_delay_measures(self):
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"""
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Write the measure statements to quantify the bitline voltage at sense amp enable 50%.
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"""
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self.sf.write("\n* Measure statements for delay and power\n")
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# Output some comments to aid where cycles start and
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for comment in self.cycle_comments:
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self.sf.write("* {}\n".format(comment))
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for read_port in self.targ_read_ports:
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self.write_bitline_measures_read_port(read_port)
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def write_bitline_measures_read_port(self, port):
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"""
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Write the measure statements to quantify the delay and power results for a read port.
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"""
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# add measure statements for delays/slews
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for dname in self.delay_meas_names:
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meas_values = self.get_delay_meas_values(dname, port)
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self.stim.gen_meas_delay(*meas_values)
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def analyze(self, probe_address, probe_data, slews, loads):
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"""Measures the bitline swing of the differential bitlines (bl/br) at 50% s_en """
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self.set_probe(probe_address, probe_data)
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self.load=max(loads)
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self.slew=max(slews)
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port = 0
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bitline_swings = {}
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self.targ_read_ports = [self.read_ports[port]]
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self.targ_write_ports = [self.write_ports[port]]
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debug.info(1,"Bitline swing test: corner {}".format(self.corner))
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(success, results)=self.run_delay_simulation()
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debug.check(success, "Bitline Failed: period {}".format(self.period))
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for mname in self.bitline_meas_names:
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bitline_swings[mname] = results[port][mname]
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debug.info(1,"Bitline values (bl/br): {}".format(bitline_swings))
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return bitline_swings
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