mirror of https://github.com/VLSIDA/OpenRAM.git
209 lines
8.6 KiB
Python
209 lines
8.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer, preferred_directions, drc
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from openram.tech import layer_properties as layer_props
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from openram import OPTS
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class rom_column_mux_array(design):
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"""
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Dynamically generated column mux array.
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Array of column mux to read the bitlines from ROM, based on the RAM column mux
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"""
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def __init__(self, name, columns, word_size, tap_spacing=4, input_layer="m2", bitline_layer="m1", sel_layer="m2"):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} word_size: {1} ".format(columns, word_size))
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self.columns = columns
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self.word_size = word_size
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self.words_per_row = int(self.columns / self.word_size)
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self.input_layer = input_layer
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self.tap_spacing = tap_spacing
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self.sel_layer = sel_layer
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self.sel_pitch = getattr(self, self.sel_layer + "_pitch")
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self.bitline_layer = bitline_layer
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if preferred_directions[self.sel_layer] == "V":
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self.via_directions = ("H", "H")
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else:
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self.via_directions = "pref"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_array()
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def create_layout(self):
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self.setup_layout_constants()
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self.place_array()
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self.add_routing()
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# Find the highest shapes to determine height before adding well
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highest = self.find_highest_coords()
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self.height = highest.y
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self.add_layout_pins()
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if "pwell" in layer:
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self.add_enclosure(self.mux_inst, "pwell")
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.columns):
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self.add_pin("bl_{}".format(i))
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for i in range(self.words_per_row):
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self.add_pin("sel_{}".format(i))
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for i in range(self.word_size):
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self.add_pin("bl_out_{}".format(i))
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self.add_pin("gnd")
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def add_modules(self):
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self.mux = factory.create(module_type="rom_column_mux", input_layer=self.input_layer, output_layer=self.bitline_layer)
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self.tap = factory.create(module_type="rom_poly_tap", add_tap=True)
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self.cell = factory.create(module_type="rom_base_cell")
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def setup_layout_constants(self):
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self.column_addr_size = int(self.words_per_row / 2)
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self.width = self.columns * self.mux.width
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3) * self.cell.width
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self.route_layer_width = drc["minwidth_{}".format(self.bitline_layer)]
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self.route_layer_pitch = drc["{0}_to_{0}".format(self.bitline_layer)]
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def create_array(self):
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self.mux_inst = []
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# For every column, add a pass gate
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for col_num in range(self.columns):
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name = "XMUX{0}".format(col_num)
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self.mux_inst.append(self.add_inst(name=name,
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mod=self.mux))
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self.connect_inst(["bl_{}".format(col_num),
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"bl_out_{}".format(int(col_num / self.words_per_row)),
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"sel_{}".format(col_num % self.words_per_row),
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"gnd"])
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def place_array(self):
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# Default to single spaced columns
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self.offsets = [n * self.mux.width for n in range(self.columns)]
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# For every column, add a pass gate
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for col_num, xoffset in enumerate(self.offsets[0:self.columns]):
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset)
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def add_layout_pins(self):
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""" Add the pins after we determine the height. """
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# For every column, add a pass gate
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for col_num in range(self.columns):
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mux_inst = self.mux_inst[col_num]
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bl_pin = mux_inst.get_pin("bl")
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offset = bl_pin.ll()
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self.add_layout_pin(text="bl_{}".format(col_num),
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layer=bl_pin.layer,
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offset=offset,
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height=self.height - offset.y)
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def route_supplies(self):
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self.route_horizontal_pins("gnd", self.insts)
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def add_routing(self):
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self.add_horizontal_input_rail()
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self.add_vertical_poly_rail()
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self.route_bitlines()
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self.route_supplies()
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def add_horizontal_input_rail(self):
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""" Create address input rails below the mux transistors """
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tap_offset = 0
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for j in range(self.words_per_row):
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if j % self.tap_spacing == 0 and j != 0:
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tap_offset += self.tap.pitch_offset
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offset = vector(0, self.route_height + tap_offset + (j - self.words_per_row) * self.cell.width)
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self.add_layout_pin(text="sel_{}".format(j),
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layer=self.sel_layer,
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offset=offset,
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width=self.mux_inst[-1].rx())
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def add_vertical_poly_rail(self):
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""" Connect the poly to the address rails """
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# Offset to the first transistor gate in the pass gate
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for col in range(self.columns):
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# which select bit should this column connect to depends on the position in the word
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sel_index = col % self.words_per_row
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# Add the column x offset to find the right select bit
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,
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self.get_pin("sel_{}".format(sel_index)).cy())
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bl_x_offset = self.mux_inst[col].get_pin("bl_out").cx() + 2 * self.route_layer_width + self.route_layer_pitch + 0.5 * self.poly_contact.width
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bl_offset = offset.scale(0, 1) + vector(bl_x_offset, 0)
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self.add_via_stack_center(from_layer="poly",
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to_layer=self.sel_layer,
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offset=bl_offset,
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directions=self.via_directions)
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self.add_path("poly", [offset, gate_offset, bl_offset])
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def route_bitlines(self):
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""" Connect the output bit-lines to form the appropriate width mux """
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for j in range(self.columns):
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bl_offset_begin = self.mux_inst[j].get_pin("bl_out").bc()
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bl_out_offset_begin = bl_offset_begin - vector(0, (self.words_per_row + 1) * self.cell.width)
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# Add the horizontal wires for the first bit
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if j % self.words_per_row == 0:
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bl_offset_end = self.mux_inst[j + self.words_per_row - 1].get_pin("bl_out").bc()
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bl_out_offset_end = bl_offset_end - vector(0, (self.words_per_row + 1) * self.cell.width)
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self.add_path(self.sel_layer, [bl_out_offset_begin, bl_out_offset_end])
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# Extend the bitline output rails and gnd downward on the first bit of each n-way mux
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self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)),
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layer=self.bitline_layer,
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start=bl_offset_begin,
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end=bl_out_offset_begin)
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else:
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self.add_path(self.bitline_layer, [bl_out_offset_begin, bl_offset_begin])
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# This via is on the right of the wire
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self.add_via_stack_center(from_layer=self.bitline_layer,
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to_layer=self.sel_layer,
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offset=bl_out_offset_begin,
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directions=self.via_directions)
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def graph_exclude_columns(self, column_include_num):
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"""
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Excludes all columns muxes unrelated to the target bit being simulated.
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Each mux in mux_inst corresponds to respective column in bitcell array.
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"""
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for i in range(len(self.mux_inst)):
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if i != column_include_num:
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self.graph_inst_exclude.add(self.mux_inst[i]) |