mirror of https://github.com/VLSIDA/OpenRAM.git
239 lines
9.0 KiB
Python
239 lines
9.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California
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# All rights reserved.
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#
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import debug
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from .bitcell_base_array import bitcell_base_array
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from sram_factory import factory
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from base import vector
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from globals import OPTS
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from tech import layer_properties as layer_props
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class replica_column(bitcell_base_array):
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"""
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Generate a replica bitline column for the replica array.
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Rows is the total number of rows in the main array.
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rbl is a tuple with the number of left and right replica bitlines.
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Replica bit specifies which replica column this is (to determine where to put the
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replica cell relative to the bottom (including the dummy bit at 0).
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"""
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def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
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# Used for pin names and properties
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self.cell = factory.create(module_type=OPTS.bitcell)
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# Row size is the number of rows with word lines
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self.row_size = sum(rbl) + rows
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# Start of regular word line rows
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self.row_start = rbl[0] + 1
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# End of regular word line rows
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self.row_end = self.row_start + rows
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if not self.cell.end_caps:
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self.row_size += 2
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super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name)
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self.rows = rows
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.replica_bit = replica_bit
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# Total size includes the replica rows and column cap rows
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self.total_size = self.left_rbl + rows + self.right_rbl + 2
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self.column_offset = column_offset
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debug.check(replica_bit != 0 and replica_bit != self.total_size - 1,
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"Replica bit cannot be the dummy/cap row.")
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debug.check(replica_bit < self.row_start or replica_bit >= self.row_end,
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"Replica bit cannot be in the regular array.")
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if layer_props.replica_column.even_rows:
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debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
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"sky130 currently requires rows to be even and to start with X mirroring"
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+ " (left_rbl must be odd) for LVS.")
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_instances()
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self.height = self.cell_inst[-1].uy()
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self.width = self.cell_inst[0].rx()
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.create_all_bitline_names()
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self.create_all_wordline_names(self.row_size)
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self.add_pin_list(self.all_bitline_names, "OUTPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.replica_cell = factory.create(module_type=OPTS.replica_bitcell)
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
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try:
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edge_module_type = ("col_cap" if self.cell.end_caps else "dummy")
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except AttributeError:
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edge_module_type = "dummy"
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self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
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def create_instances(self):
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self.cell_inst = []
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for row in range(self.total_size):
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name="rbc_{0}".format(row)
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real_row = row
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if self.cell.end_caps:
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real_row -= 1
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# Regular array cells are replica cells
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# Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell.
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if (row == 0 or row == self.total_size - 1):
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self.cell_inst.append(self.add_inst(name=name,
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mod=self.edge_cell))
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if self.cell.end_caps:
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self.connect_inst(self.get_bitcell_pins_col_cap(real_row, 0))
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else:
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self.connect_inst(self.get_bitcell_pins(real_row, 0))
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elif (row==self.replica_bit) or (row >= self.row_start and row < self.row_end):
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self.cell_inst.append(self.add_inst(name=name,
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mod=self.replica_cell))
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self.connect_inst(self.get_bitcell_pins(real_row, 0))
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else:
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# Top/bottom cell are always dummy/cap cells.
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self.cell_inst.append(self.add_inst(name=name,
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mod=self.dummy_cell))
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self.connect_inst(self.get_bitcell_pins(real_row, 0))
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def place_instances(self):
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# Flip the mirrors if we have an odd number of replica+dummy rows at the bottom
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# so that we will start with mirroring rather than not mirroring
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rbl_offset = (self.left_rbl + 1) %2
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# if our bitcells are mirrored on the y axis, check if we are in global
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# column that needs to be flipped.
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dir_y = False
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xoffset = 0
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if self.cell.mirror.y and self.column_offset % 2:
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dir_y = True
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xoffset = self.replica_cell.width
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for row in range(self.total_size):
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# name = "bit_r{0}_{1}".format(row, "rbl")
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dir_x = self.cell.mirror.x and (row + rbl_offset) % 2
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offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row].place(offset=offset,
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mirror=dir_key)
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def add_layout_pins(self):
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""" Add the layout pins """
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for port in self.all_ports:
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bl_pin = self.cell_inst[0].get_pin(self.cell.get_bl_name(port))
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self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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bl_pin = self.cell_inst[0].get_pin(self.cell.get_br_name(port))
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self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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if self.cell.end_caps:
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row_range_max = self.total_size - 1
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row_range_min = 1
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else:
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row_range_max = self.total_size
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row_range_min = 0
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for port in self.all_ports:
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for row in range(row_range_min, row_range_max):
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wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row - row_range_min),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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def route_supplies(self):
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for inst in self.cell_inst:
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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def get_bitline_names(self, port=None):
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if port == None:
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return self.all_bitline_names
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else:
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return self.bitline_names[port]
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def get_bitcell_pins(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def get_bitcell_pins_col_cap(self, row, col):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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if len(self.edge_cell.get_pins("vdd")) > 0:
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bitcell_pins.append("vdd")
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if len(self.edge_cell.get_pins("gnd")) > 0:
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bitcell_pins.append("gnd")
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return bitcell_pins
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def exclude_all_but_replica(self):
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"""
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Excludes all bits except the replica cell (self.replica_bit).
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"""
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for row, cell in enumerate(self.cell_inst):
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if row != self.replica_bit:
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self.graph_inst_exclude.add(cell)
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