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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 02:57:53 +02:00
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7e091fc6224eedbf98ae598c177eb4d21ae6ef41
OpenRAM/compiler/tests/golden
T
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Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes.
Changes propagate through all designs.
All modules use instance and layout pins.
2017-12-12 15:04:01 -08:00
..
sram_2_16_1_freepdk45_analytical.lib
Two bank SRAMs working in both technologies.
2017-09-29 16:22:13 -07:00
sram_2_16_1_freepdk45.lef
Rewrite the parameterized transistor and gate classes.
2017-12-12 15:04:01 -08:00
sram_2_16_1_freepdk45.lib
Rewrite the parameterized transistor and gate classes.
2017-12-12 15:04:01 -08:00
sram_2_16_1_freepdk45.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sram_2_16_1_freepdk45.v
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sram_2_16_1_scn3me_subm_analytical.lib
Rewrite the parameterized transistor and gate classes.
2017-12-12 15:04:01 -08:00
sram_2_16_1_scn3me_subm.lef
Rewrite the parameterized transistor and gate classes.
2017-12-12 15:04:01 -08:00
sram_2_16_1_scn3me_subm.lib
Rewrite the parameterized transistor and gate classes.
2017-12-12 15:04:01 -08:00
sram_2_16_1_scn3me_subm.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sram_2_16_1_scn3me_subm.v
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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