mirror of https://github.com/VLSIDA/OpenRAM.git
126 lines
4.5 KiB
Python
126 lines
4.5 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2022 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.base import design
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from openram.base import vector
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from openram.sram_factory import factory
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from openram.tech import layer
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from openram import OPTS
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class and3_dec(design):
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"""
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This is an AND with configurable drive strength.
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"""
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def __init__(self, name, size=1, height=None, add_wells=True):
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design.__init__(self, name)
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debug.info(1, "Creating and3_dec {}".format(name))
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self.add_comment("size: {}".format(size))
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self.size = size
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self.height = height
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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self.nand = factory.create(module_type="nand3_dec",
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height=self.height)
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self.inv = factory.create(module_type="inv_dec",
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height=self.height,
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size=self.size)
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def create_layout(self):
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if "li" in layer:
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self.route_layer = "li"
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else:
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self.route_layer = "m1"
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self.width = self.nand.width + self.inv.width
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self.height = self.nand.height
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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self.route_supply_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin("A", "INPUT")
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self.add_pin("B", "INPUT")
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self.add_pin("C", "INPUT")
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self.add_pin("Z", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_insts(self):
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self.nand_inst = self.add_inst(name="pand3_dec_nand",
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mod=self.nand)
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self.connect_inst(["A", "B", "C", "zb_int", "vdd", "gnd"])
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self.inv_inst = self.add_inst(name="pand3_dec_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0, 0))
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# Add INV to the right
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self.inv_inst.place(offset=vector(self.nand_inst.rx(), 0))
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def route_supply_rails(self):
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""" Add vdd/gnd rails to the top, (middle), and bottom. """
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if OPTS.tech_name == "sky130":
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for name in ["vdd", "gnd"]:
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for inst in [self.nand_inst, self.inv_inst]:
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self.copy_layout_pin(inst, name)
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else:
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self.add_layout_pin_rect_center(text="gnd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, 0),
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width=self.width)
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self.add_layout_pin_rect_center(text="vdd",
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layer=self.route_layer,
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offset=vector(0.5 * self.width, self.height),
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width=self.width)
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def add_wires(self):
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# nand Z to inv A
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z1_pin = self.nand_inst.get_pin("Z")
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a2_pin = self.inv_inst.get_pin("A")
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if OPTS.tech_name == "sky130":
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mid1_point = vector(a2_pin.cx(), z1_pin.cy())
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else:
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mid1_point = vector(z1_pin.cx(), a2_pin.cy())
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self.add_path(self.route_layer,
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[z1_pin.center(), mid1_point, a2_pin.center()])
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def add_layout_pins(self):
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pin = self.inv_inst.get_pin("Z")
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self.add_layout_pin_rect_center(text="Z",
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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for pin_name in ["A", "B", "C"]:
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pin = self.nand_inst.get_pin(pin_name)
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=pin.height())
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