mirror of https://github.com/VLSIDA/OpenRAM.git
227 lines
11 KiB
Python
227 lines
11 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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from tech import cell_properties
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from sram_factory import factory
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from globals import OPTS
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class bitcell_base_array(design.design):
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"""
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Abstract base class for bitcell-arrays -- bitcell, dummy, replica
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"""
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def __init__(self, name, rows, cols, column_offset):
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super().__init__(name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.column_offset = column_offset
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# Bitcell for port names only
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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else:
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self.cell = factory.create(module_type="s8_bitcell", version="opt1")
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self.cell2 = factory.create(module_type="s8_bitcell", version="opt1a")
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self.strap = factory.create(module_type="s8_internal", version="wlstrap")
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self.strap2 = factory.create(module_type="s8_internal", version="wlstrap_p")
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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def get_all_bitline_names(self, prefix=""):
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return [prefix + x for x in self.all_bitline_names]
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def create_all_bitline_names(self):
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self.bitline_names = [[] for port in self.all_ports]
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for col in range(self.column_size):
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for port in self.all_ports:
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self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col),
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"br_{0}_{1}".format(port, col)])
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def get_all_wordline_names(self, prefix=""):
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return [prefix + x for x in self.all_wordline_names]
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def create_all_wordline_names(self):
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self.wordline_names = [[] for port in self.all_ports]
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for row in range(self.row_size):
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for port in self.all_ports:
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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else:
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self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
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self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def get_bitline_names(self, port=None):
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if port == None:
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return self.all_bitline_names
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else:
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return self.bitline_names[port]
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def get_wordline_names(self, port=None):
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if port == None:
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return self.all_wordline_names
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else:
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return self.wordline_names[port]
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def add_pins(self):
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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else:
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def add_layout_pins(self):
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""" Add the layout pins """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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height=wl_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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else:
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl0_{0}_{1}".format(port, col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="bl1_{0}_{1}".format(port, col),
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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for row in range(self.row_size):
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for port in self.all_ports:
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wl0_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl0_{0}_{1}".format(port, row),
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layer=wl0_pin.layer,
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offset=wl0_pin.ll().scale(0, 1),
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width=self.width,
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height=wl0_pin.height())
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wl1_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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self.add_layout_pin(text="wl1_{0}_{1}".format(port, row),
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layer=wl1_pin.layer,
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offset=wl1_pin.ll().scale(0, 1),
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width=self.width,
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height=wl1_pin.height())
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# Copy a vdd/gnd layout pin from every cell
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vpwr", "vgnd"]:
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self.copy_layout_pin(inst, pin_name)
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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dir_y = False
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# If we mirror the current cell on the y axis adjust the x position
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if cell_properties.bitcell.mirror.y and (col + col_offset) % 2:
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tempx = xoffset + self.cell.width
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dir_y = True
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return (tempx, dir_y)
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def _adjust_y_offset(self, yoffset, row, row_offset):
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tempy = yoffset
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dir_x = False
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# If we mirror the current cell on the x axis adjust the y position
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if cell_properties.bitcell.mirror.x and (row + row_offset) % 2:
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tempy = yoffset + self.cell.height
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dir_x = True
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return (tempy, dir_x)
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
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for row in range(self.row_size):
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tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
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if dir_x and dir_y:
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dir_key = "XY"
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elif dir_x:
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dir_key = "MX"
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elif dir_y:
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dir_key = "MY"
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else:
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dir_key = ""
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self.cell_inst[row, col].place(offset=[tempx, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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else:
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from tech import custom_cell_placement
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custom_cell_placement(self)
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