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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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7c3375fd4be0d33b5e900cbc6c736a01953cdaa9
OpenRAM/compiler/bitcells
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Michael Timothy Grimes 7c3375fd4b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
2018-11-08 09:59:52 -08:00
..
bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
pbitcell.py
Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell.
2018-11-02 05:59:47 -07:00
replica_bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
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