luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
7b270514e1b528a76bdcf1729383f88e79665b2f
OpenRAM/compiler/tests
T
History
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
2021-03-23 10:45:56 -07:00
..
configs
Update copyright year.
2021-01-22 11:23:28 -08:00
golden
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
00_code_format_check_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
01_library_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_contact_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_path_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_1finger_nmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_1finger_pmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_3finger_nmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_3finger_pmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_4finger_nmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_4finger_pmos_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_ptx_no_contacts_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
03_wire_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_and2_dec_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_and3_dec_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_and4_dec_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_column_mux_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_column_mux_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_column_mux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_dff_buf_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_dummy_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pand2_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pand3_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pand4_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pbuf_dec_8x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pbuf_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pdriver_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_1x_beta_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_1x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_2x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_10x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_100x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinv_dec_1x_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pinvbuf_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pnand2_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pnand3_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pnand4_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pnor2_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_precharge_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_precharge_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_precharge_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_pwrite_driver_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_replica_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
04_wordline_driver_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
05_bitcell_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
05_bitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
05_dummy_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
05_pbitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_decoder_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_decoder_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_decoder_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode2x4_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode2x4_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode2x4_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode3x8_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode3x8_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode3x8_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
06_hierarchical_predecode4x16_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
07_column_mux_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
07_column_mux_array_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
07_column_mux_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_precharge_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_precharge_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_wordline_buffer_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_wordline_driver_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_wordline_driver_array_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
08_wordline_driver_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
09_sense_amp_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
09_sense_amp_array_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
09_sense_amp_array_test_pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
09_sense_amp_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_wmask_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_wmask_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_driver_array_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_mask_and_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_mask_and_array_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
10_write_mask_and_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
11_dff_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
11_dff_buf_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
12_tri_gate_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
13_delay_chain_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
14_replica_bitcell_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
14_replica_bitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
14_replica_column_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
14_replica_column_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
14_replica_pbitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
15_global_bitcell_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
15_global_bitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
15_local_bitcell_array_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
15_local_bitcell_array_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
16_control_logic_multiport_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
16_control_logic_r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
16_control_logic_rw_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
16_control_logic_w_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_address_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_address_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_data_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_data_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_data_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_data_wmask_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
18_port_data_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_bank_select_pbitcell_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_bank_select_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_multi_bank_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_pmulti_bank_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_psingle_bank_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_1w_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_global_bitline.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_wmask_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
19_single_bank_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_psram_1bank_2mux_1rw_1w_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_psram_1bank_2mux_1rw_1w_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_psram_1bank_2mux_1w_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_psram_1bank_2mux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_psram_1bank_4mux_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_1rw_1r_test.py
Merge branch 'supply_router' into dev
2021-01-25 11:01:48 -08:00
20_sram_1bank_2mux_1w_1r_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_1w_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_global_test.py
Merge branch 'supply_router' into dev
2021-01-25 11:01:48 -08:00
20_sram_1bank_2mux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_wmask_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_2mux_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_4mux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_8mux_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_8mux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_32b_1024_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_1rw_1r_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_spare_cols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_wmask_sparecols_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_1bank_nomux_wmask_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
20_sram_2bank_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
21_hspice_delay_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
21_hspice_setuphold_test.py
Skywater changes.
2021-03-22 15:48:14 -07:00
21_model_delay_test.py
Merge branch 'dev' into automated_analytical_model
2021-02-01 01:49:45 -08:00
21_ngspice_delay_extra_rows_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
21_ngspice_delay_global_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
21_ngspice_delay_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
21_ngspice_setuphold_test.py
Skywater changes.
2021-03-22 15:48:14 -07:00
22_psram_1bank_2mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_psram_1bank_4mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_psram_1bank_8mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_psram_1bank_nomux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_2mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_2mux_global_func_test.py
Merge branch 'supply_router' into dev
2021-01-25 11:01:48 -08:00
22_sram_1bank_2mux_sparecols_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_4mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_8mux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_nomux_1rw_1r_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_nomux_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_nomux_sparecols_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_1bank_wmask_1rw_1r_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
22_sram_wmask_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
23_lib_sram_linear_regression_test.py
Added test for linear regression model.
2020-12-14 14:37:53 -08:00
23_lib_sram_model_corners_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
23_lib_sram_model_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
23_lib_sram_prune_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
23_lib_sram_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
24_lef_sram_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
25_verilog_sram_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
26_hspice_pex_pinv_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
26_ngspice_pex_pinv_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
26_sram_pex_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
30_openram_back_end_test.py
Update multithreaded regression.
2021-03-23 10:45:56 -07:00
30_openram_front_end_test.py
Update multithreaded regression.
2021-03-23 10:45:56 -07:00
50_riscv_func_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
50_riscv_phys_test.py
Update copyright year.
2021-01-22 11:23:28 -08:00
regress.py
Skywater changes.
2021-03-22 15:48:14 -07:00
skip_tests_sky130.txt
Default zom is None not negative.
2020-12-15 13:27:36 -08:00
sram_1rw_1r_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_wmask_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
testutils.py
Skywater changes.
2021-03-22 15:48:14 -07:00