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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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7aafa438978cd4f38afa501d40357ddea0593ce6
OpenRAM/compiler/pgates
T
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mrg b2b7e7800b Undo same bitline pitch
2020-06-03 16:39:05 -07:00
..
pand2.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pand3.py
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
pbuf.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pdriver.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pgate.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pinv_dec.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pinv.py
Check min size inverter.
2020-05-13 16:54:26 -07:00
pinvbuf.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
pnand2.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
pnand3.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pnor2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
precharge.py
Undo same bitline pitch
2020-06-03 16:39:05 -07:00
ptristate_inv.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptx.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pwrite_driver.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
single_level_column_mux.py
Fix the bitline spacing in the column mux to a constant.
2020-06-03 15:47:03 -07:00
wordline_driver.py
Hard cells can accept height parameter too.
2020-06-01 16:46:00 -07:00
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