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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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78be7248673d7403d4c910eaec05204a0a39547d
OpenRAM/compiler/characterizer
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Hunter Nichols 78be724867 Edited find_feasible period to use dynamic naming on its measured values and edited the algorithm to work with multiport.
2018-08-30 00:11:14 -07:00
..
__init__.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Edited find_feasible period to use dynamic naming on its measured values and edited the algorithm to work with multiport.
2018-08-30 00:11:14 -07:00
lib.py
Changed create_test_cycles to have targeted ports for characterization rather than all ports always.
2018-08-29 17:16:11 -07:00
setup_hold.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
stimuli.py
Fixed naming issue between sram instance and PWL in stimulus
2018-08-28 12:09:02 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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