mirror of https://github.com/VLSIDA/OpenRAM.git
108 lines
3.4 KiB
Python
108 lines
3.4 KiB
Python
#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 19_psingle_bank_test")
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class psingle_bank_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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global verify
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import verify
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from bank import bank
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OPTS.bitcell = "pbitcell"
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# testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
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OPTS.rw_ports = 1
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OPTS.w_ports = 0
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OPTS.r_ports = 0
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_1rw_0w_0r_single")
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self.local_check(a)
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"""
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# testing all port configurations (with no column mux) to verify layout between bitcell array and peripheral circuitry
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OPTS.rw_ports = 2
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OPTS.w_ports = 2
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OPTS.r_ports = 2
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# multiport can't generate layout yet on the bank level
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OPTS.netlist_only = True
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_2rw_2w_2r_single")
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self.local_check(a)
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"""
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"""
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OPTS.rw_ports = 0
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OPTS.w_ports = 2
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OPTS.r_ports = 2
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_0rw_2w_2r_single")
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self.local_check(a)
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OPTS.rw_ports = 2
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OPTS.w_ports = 0
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OPTS.r_ports = 2
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_2rw_0w_2r_single")
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self.local_check(a)
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OPTS.rw_ports = 2
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OPTS.w_ports = 2
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OPTS.r_ports = 0
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_2rw_2w_0r_single")
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self.local_check(a)
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OPTS.rw_ports = 2
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OPTS.w_ports = 0
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OPTS.r_ports = 0
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debug.info(1, "No column mux")
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a = bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="bank1_2rw_0w_0r_single")
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self.local_check(a)
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# testing with various column muxes
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OPTS.rw_ports = 2
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OPTS.w_ports = 2
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OPTS.r_ports = 2
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debug.info(1, "Two way column mux")
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a = bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="bank2_single")
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self.local_check(a)
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debug.info(1, "Four way column mux")
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a = bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="bank3_single")
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self.local_check(a)
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# Eight way has a short circuit of one column mux select to gnd rail
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debug.info(1, "Eight way column mux")
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a = bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="bank4_single")
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self.local_check(a)
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"""
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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