mirror of https://github.com/VLSIDA/OpenRAM.git
246 lines
7.6 KiB
Python
Executable File
246 lines
7.6 KiB
Python
Executable File
import os
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"""
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File containing the process technology parameters for SCMOS 3me, subm, 180nm.
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"""
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info={}
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info["name"]="scn3me_subm"
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info["body_tie_down"] = 0
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info["has_pwell"] = True
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info["has_nwell"] = True
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#GDS file info
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GDS={}
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# gds units
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GDS["unit"]=(0.001,1e-6)
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# default label zoom
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GDS["zoom"] = 0.5
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###################################################
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##GDS Layer Map
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###################################################
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# create the GDS layer map
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layer={}
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layer["vtg"] = -1
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layer["vth"] = -1
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layer["contact"] = 47
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layer["pwell"] = 41
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layer["nwell"] = 42
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layer["active"] = 43
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layer["pimplant"] = 44
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layer["nimplant"] = 45
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layer["poly"] = 46
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layer["active_contact"] = 48
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layer["metal1"] = 49
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layer["via1"] = 50
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layer["metal2"] = 51
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layer["via2"] = 61
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layer["metal3"] = 62
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layer["text"] = 83
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layer["boundary"] = 83
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###################################################
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##END GDS Layer Map
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###################################################
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###################################################
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##DRC/LVS Rules Setup
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###################################################
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 1.2
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parameter["beta"] = 2
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc={}
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#grid size is 1/2 a lambda
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drc["grid"]=0.15
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
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# minwidth_tx with contact (no dog bone transistors)
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drc["minwidth_tx"] = 1.2
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drc["minlength_channel"] = 0.6
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# 1.4 Minimum spacing between wells of different type (if both are drawn)
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drc["pwell_to_nwell"] = 0
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# 1.1 Minimum width
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drc["minwidth_well"] = 3.6
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# 3.1 Minimum width
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drc["minwidth_poly"] = 0.6
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# 3.2 Minimum spacing over active
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drc["poly_to_poly"] = 0.9
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# 3.3 Minimum gate extension of active
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drc["poly_extend_active"] = 0.6
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# ??
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drc["poly_to_polycontact"] = 1.2
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# ??
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drc["active_enclosure_gate"] = 0.0
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# 3.2.a Minimum spacing over field poly
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drc["poly_to_field_poly"] = 0.9
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# 3.5 Minimum field poly to active
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drc["poly_to_active"] = 0.3
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# Not a rule
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drc["minarea_poly"] = 0.0
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# ??
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drc["active_to_body_active"] = 1.2 # Fix me
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# 2.1 Minimum width
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drc["minwidth_active"] = 0.9
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# 2.2 Minimum spacing
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drc["active_to_active"] = 0.9
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# 2.3 Source/drain active to well edge
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drc["well_enclosure_active"] = 1.8
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# Reserved for asymmetric enclosures
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drc["well_extend_active"] = 1.8
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# Not a rule
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drc["minarea_active"] = 0.0
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# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
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drc["implant_to_channel"] = 0.9
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# 4.2 Minimum select overlap of active
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drc["implant_enclosure_active"] = 0.6
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# 4.3 Minimum select overlap of contact
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drc["implant_enclosure_contact"] = 0.3
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# Not a rule
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drc["implant_to_contact"] = 0
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# Not a rule
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drc["implant_to_implant"] = 0
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# Not a rule
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drc["minwidth_implant"] = 0
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# 6.1 Exact contact size
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drc["minwidth_contact"] = 0.6
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# 5.3 Minimum contact spacing
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drc["contact_to_contact"] = 0.9
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# 6.2.b Minimum active overlap
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drc["active_enclosure_contact"] = 0.3
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# Reserved for asymmetric enclosure
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drc["active_extend_contact"] = 0.3
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# 5.2.b Minimum poly overlap
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drc["poly_enclosure_contact"] = 0.3
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# Reserved for asymmetric enclosures
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drc["poly_extend_contact"] = 0.3
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# Reserved for other technologies
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drc["contact_to_gate"] = 0.6
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# 5.4 Minimum spacing to gate of transistor
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drc["contact_to_poly"] = 0.6
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# 7.1 Minimum width
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drc["minwidth_metal1"] = 0.9
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# 7.2 Minimum spacing
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drc["metal1_to_metal1"] = 0.9
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# 7.3 Minimum overlap of any contact
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drc["metal1_enclosure_contact"] = 0.3
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# Reserved for asymmetric enclosure
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drc["metal1_extend_contact"] = 0.3
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# 8.3 Minimum overlap by metal1
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drc["metal1_enclosure_via1"] = 0.3
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# Reserve for asymmetric enclosures
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drc["metal1_extend_via1"] = 0.3
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# Not a rule
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drc["minarea_metal1"] = 0
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# 8.1 Exact size
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drc["minwidth_via1"] = 0.6
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# 8.2 Minimum via1 spacing
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drc["via1_to_via1"] = 0.6
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# 9.1 Minimum width
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drc["minwidth_metal2"] = 0.9
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# 9.2 Minimum spacing
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drc["metal2_to_metal2"] = 0.9
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# 9.3 Minimum overlap of via1
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drc["metal2_extend_via1"] = 0.3
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via1"] = 0.3
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# 14.3 Minimum overlap by metal2
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drc["metal2_extend_via2"] = 0.3
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# Reserved for asymmetric enclosures
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drc["metal2_enclosure_via2"] = 0.3
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# Not a rule
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drc["minarea_metal2"] = 0
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# 14.2 Exact size
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drc["minwidth_via2"] = 0.6
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# 14.2 Minimum spacing
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drc["via2_to_via2"] = 0.9
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# 15.1 Minimum width
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drc["minwidth_metal3"] = 1.5
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# 15.2 Minimum spacing to metal3
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drc["metal3_to_metal3"] = 0.9
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# 15.3 Minimum overlap of via 2
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drc["metal3_extend_via2"] = 0.6
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# Reserved for asymmetric enclosures
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drc["metal3_enclosure_via2"] = 0.6
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# Not a rule
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drc["minarea_metal3"] = 0
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###################################################
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##END DRC/LVS Rules
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###################################################
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###################################################
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##Spice Simulation Parameters
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###################################################
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# spice model info
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spice={}
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spice["nmos"]="n"
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spice["pmos"]="p"
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# This is a map of corners to model files
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SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
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# FIXME: Uncomment when we have the new spice models
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#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
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spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
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"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
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"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
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"SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
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"SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] }
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#spice stimulus related variables
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spice["feasible_period"] = 5 # estimated feasible period in ns
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spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
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spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
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spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
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spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
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#sram signal names
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#FIXME: We don't use these everywhere...
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spice["vdd_name"] = "vdd"
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spice["gnd_name"] = "gnd"
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spice["control_signals"] = ["CSb", "WEb", "OEb"]
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spice["data_name"] = "DATA"
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spice["addr_name"] = "ADDR"
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spice["minwidth_tx"] = drc["minwidth_tx"]
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spice["channel"] = drc["minlength_channel"]
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spice["clk"] = "clk"
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# analytical delay parameters
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# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
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spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
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spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
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spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
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spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
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spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
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spice["msflop_setup"] = 9 # DFF setup time in ps
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spice["msflop_hold"] = 1 # DFF hold time in ps
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spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
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spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
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spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
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###################################################
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##END Spice Simulation Parameters
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###################################################
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