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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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763f1e8deea8eef0169903842df1dc0255a4ae69
OpenRAM
/
technology
/
scn3me_subm
T
History
Matt Guthaus
763f1e8dee
Finish renaming replica bitcell and bitline pin names.
2018-09-04 14:03:15 -07:00
..
gds_lib
Finish renaming replica bitcell and bitline pin names.
2018-09-04 14:03:15 -07:00
mag_lib
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
models
Remove KP from SCMOS models to get rid of ngspice error.
2018-03-01 11:10:04 -08:00
sp_lib
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
tf
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
