mirror of https://github.com/VLSIDA/OpenRAM.git
128 lines
4.6 KiB
Python
128 lines
4.6 KiB
Python
import design
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from tech import drc
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from vector import vector
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import debug
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from globals import OPTS
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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Dynamically generated sense amp array for all bitlines.
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"""
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def __init__(self, word_size, words_per_row):
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design.design.__init__(self, "sense_amp_array")
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debug.info(1, "Creating {0}".format(self.name))
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.row_size = self.word_size * self.words_per_row
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_sense_amp_array()
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def create_layout(self):
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self.height = self.amp.height
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self.width = self.amp.width * self.word_size * self.words_per_row
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self.place_sense_amp_array()
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self.add_layout_pins()
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self.route_rails()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(0,self.word_size):
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self.add_pin("data[{0}]".format(i))
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self.add_pin("bl[{0}]".format(i))
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self.add_pin("br[{0}]".format(i))
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self.add_pin("en")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.sense_amp))
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self.mod_sense_amp = getattr(c, OPTS.sense_amp)
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self.amp = self.mod_sense_amp("sense_amp")
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self.add_mod(self.amp)
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0,self.word_size):
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name = "sa_d{0}".format(i)
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self.local_insts.append(self.add_inst(name=name,
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mod=self.amp))
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self.connect_inst(["bl[{0}]".format(i),
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"br[{0}]".format(i),
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"data[{0}]".format(i),
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"en", "vdd", "gnd"])
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def place_sense_amp_array(self):
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amp_spacing = self.amp.width * self.words_per_row
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for i in range(0,self.word_size):
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amp_position = vector(amp_spacing * i, 0)
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self.local_insts[i].place(amp_position)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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gnd_pos = inst.get_pin("gnd").center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=gnd_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal3",
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offset=gnd_pos)
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vdd_pos = inst.get_pin("vdd").center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pos)
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pos)
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bl_pin = inst.get_pin("bl")
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br_pin = inst.get_pin("br")
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dout_pin = inst.get_pin("dout")
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self.add_layout_pin(text="bl[{0}]".format(i),
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layer="metal2",
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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self.add_layout_pin(text="br[{0}]".format(i),
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layer="metal2",
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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self.add_layout_pin(text="data[{0}]".format(i),
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layer="metal2",
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# add sclk rail across entire array
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sclk_offset = self.amp.get_pin("en").ll().scale(0,1)
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self.add_layout_pin(text="en",
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layer="metal1",
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offset=sclk_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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def analytical_delay(self, slew, load=0.0):
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return self.amp.analytical_delay(slew=slew, load=load)
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