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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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7461f2b1bfa3aa1b3088c16d289bfe76f157d685
OpenRAM/technology/freepdk45
T
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Hunter Nichols 7461f2b1bf Merged with dev.
2018-11-02 17:22:09 -07:00
..
gds_lib
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sp_lib
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
tech
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
tf
Change layer text to comment to avoid glade reserved keyword
2018-11-02 10:58:00 -07:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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