mirror of https://github.com/VLSIDA/OpenRAM.git
23 lines
669 B
Python
23 lines
669 B
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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from .bitcell_base import bitcell_base
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class row_cap_bitcell_1port(bitcell_base):
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"""
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Row end cap cell.
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"""
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def __init__(self, name="row_cap_bitcell_1port"):
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bitcell_base.__init__(self, name, prop=props.row_cap_1port)
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debug.info(2, "Create row_cap bitcell 1 port object")
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self.no_instances = True
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