mirror of https://github.com/VLSIDA/OpenRAM.git
91 lines
3.4 KiB
Python
91 lines
3.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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#!/usr/bin/env python3
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"Run a regresion test the library cells for DRC"
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],"../.."))
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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OPTS = globals.OPTS
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class big_test(openram_test):
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"""
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Simplest two pin route test with no blockages using the pin locations instead of labels.
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"""
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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from gds_cell import gds_cell
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from design import design
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from signal_router import signal_router as router
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class routing(design, openram_test):
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"""
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A generic GDS design that we can route on.
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"""
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def __init__(self, name):
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design.__init__(self, "top")
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# Instantiate a GDS cell with the design
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gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name)
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cell = gds_cell(name, gds_file)
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self.add_inst(name=name,
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mod=cell,
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offset=[0,0])
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self.connect_inst([])
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layer_stack =("metal1","via1","metal2")
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r=router(layer_stack,self,gds_file)
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connections=[('out_0_2', 'a_0_0'),
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('out_0_3', 'b_0_0'),
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('out_0_0', 'a_0_1'),
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('out_1_2', 'a_1_0'),
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('out_1_3', 'b_1_0'),
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('out_1_0', 'a_1_1'),
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('out_2_1', 'a_2_0'),
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('out_2_2', 'b_2_0'),
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('out_3_1', 'a_3_0'),
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('out_3_2', 'b_3_0'),
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('out_4_6', 'a_4_0'),
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('out_4_7', 'b_4_0'),
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('out_4_8', 'a_4_2'),
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('out_4_9', 'b_4_2'),
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('out_4_10', 'a_4_4'),
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('out_4_11', 'b_4_4'),
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('out_4_0', 'a_4_1'),
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('out_4_2', 'b_4_1'),
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('out_4_4', 'a_4_5'),
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('out_4_1', 'a_4_3'),
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('out_4_5', 'b_4_3')]
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for (src,tgt) in connections:
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self.assertTrue(r.route(src=src,dest=tgt))
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# This test only runs on scn3me_subm tech
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if OPTS.tech_name=="scn3me_subm":
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r = routing("07_big_test_{0}".format(OPTS.tech_name))
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self.local_drc_check(r)
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else:
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debug.warning("This test does not support technology {0}".format(OPTS.tech_name))
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# fails if there are any DRC errors on any cells
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globals.end_openram()
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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