mirror of https://github.com/VLSIDA/OpenRAM.git
227 lines
9.0 KiB
Python
227 lines
9.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc, spice
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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import logical_effort
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class bitcell_array(design.design):
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"""
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Creates a rows x cols array of memory cells. Assumes bit-lines
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and word line is connected by abutment.
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Connects the word lines and bit lines.
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"""
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def __init__(self, cols, rows, name):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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#self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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self.height = self.row_size*self.cell.height
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self.width = self.column_size*self.cell.width
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xoffset = 0.0
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for col in range(self.column_size):
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yoffset = 0.0
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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if row % 2:
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tempy = yoffset + self.cell.height
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dir_key = "MX"
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else:
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tempy = yoffset
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dir_key = ""
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self.cell_inst[row,col].place(offset=[xoffset, tempy],
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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self.add_pin(cell_column+"_{0}".format(col))
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for row in range(self.row_size):
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for cell_row in row_list:
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self.add_pin(cell_row+"_{0}".format(row))
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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""" Add the modules used in this design """
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = []
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pin_names = self.cell.list_all_bitline_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(col))
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pin_names = self.cell.list_all_wl_names()
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for pin in pin_names:
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bitcell_pins.append(pin+"_{0}".format(row))
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bitcell_pins.append("vdd")
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bitcell_pins.append("gnd")
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return bitcell_pins
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.list_bitcell_pins(col, row))
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def add_layout_pins(self):
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""" Add the layout pins """
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row_list = self.cell.list_all_wl_names()
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column_list = self.cell.list_all_bitline_names()
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for col in range(self.column_size):
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for cell_column in column_list:
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bl_pin = self.cell_inst[0,col].get_pin(cell_column)
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self.add_layout_pin(text=cell_column+"_{0}".format(col),
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1,0),
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width=bl_pin.width(),
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height=self.height)
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for row in range(self.row_size):
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for cell_row in row_list:
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wl_pin = self.cell_inst[row,0].get_pin(cell_row)
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self.add_layout_pin(text=cell_row+"_{0}".format(row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0,1),
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width=self.width,
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
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def analytical_delay(self, corner, slew, load):
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"""Returns relative delay of the bitline in the bitcell array"""
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from tech import parameter
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#The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
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#The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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wire_unit_load = .05 * drain_load #Wires add 5% to this.
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bitline_load = (drain_load+wire_unit_load)*self.row_size
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return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_rate"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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#Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(corner, load)
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#Leakage power grows with entire array and bitlines.
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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if OPTS.netlist_only:
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width = 0
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else:
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width = self.width
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wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1"))
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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if OPTS.netlist_only:
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height = 0
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else:
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height = self.height
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1"))
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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bitcell_wl_cin = self.cell.get_wl_cin()
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total_cin = bitcell_wl_cin * self.column_size
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return total_cin
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def graph_exclude_bits(self, targ_row, targ_col):
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"""Excludes bits in column from being added to graph except target"""
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#Function is not robust with column mux configurations
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for row in range(self.row_size):
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for col in range(self.column_size):
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if row == targ_row and col == targ_col:
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continue
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self.graph_inst_exclude.add(self.cell_inst[row,col])
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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return inst_name+'.x'+self.cell_inst[row,col].name, self.cell_inst[row,col] |