mirror of https://github.com/VLSIDA/OpenRAM.git
108 lines
4.0 KiB
Python
108 lines
4.0 KiB
Python
import hierarchy_layout
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import hierarchy_spice
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import globals
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import verify
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import debug
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import os
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from globals import OPTS
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class design(hierarchy_spice.spice, hierarchy_layout.layout):
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"""
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Design Class for all modules to inherit the base features.
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Class consisting of a set of modules and instances of these modules
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"""
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name_map = []
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def __init__(self, name):
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self.gds_file = OPTS.openram_tech + "gds_lib/" + name + ".gds"
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self.sp_file = OPTS.openram_tech + "sp_lib/" + name + ".sp"
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self.name = name
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hierarchy_layout.layout.__init__(self, name)
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hierarchy_spice.spice.__init__(self, name)
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self.setup_drc_constants()
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# Check if the name already exists, if so, give an error
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# because each reference must be a unique name.
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ok_list = ['ms_flop.ms_flop', 'bitcell.bitcell', 'contact.contact',
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'ptx.ptx', 'sram.sram',
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'hierarchical_predecode2x4.hierarchical_predecode2x4',
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'hierarchical_predecode3x8.hierarchical_predecode3x8']
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if name not in design.name_map:
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design.name_map.append(name)
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elif str(self.__class__) in ok_list:
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pass
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else:
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debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1)
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def setup_drc_constants(self):
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""" These are some DRC constants used in many places in the compiler."""
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from tech import drc
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self.poly_width = drc["minwidth_poly"]
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self.poly_space = drc["poly_to_poly"]
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self.m1_width = drc["minwidth_metal1"]
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self.m1_space = drc["metal1_to_metal1"]
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self.m2_width = drc["minwidth_metal2"]
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self.m2_space = drc["metal2_to_metal2"]
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self.m3_width = drc["minwidth_metal3"]
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self.m3_space = drc["metal3_to_metal3"]
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def get_layout_pins(self,inst):
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""" Return a map of pin locations of the instance offset """
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# find the instance
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for i in self.insts:
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if i.name == inst.name:
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break
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else:
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debug.error("Couldn't find instance {0}".format(inst_name),-1)
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inst_map = inst.mod.pin_map
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return inst_map
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def DRC_LVS(self):
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"""Checks both DRC and LVS for a module"""
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if OPTS.check_lvsdrc:
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tempspice = OPTS.openram_temp + "/temp.sp"
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tempgds = OPTS.openram_temp + "/temp.gds"
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self.sp_write(tempspice)
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self.gds_write(tempgds)
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debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
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debug.check(verify.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name))
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os.remove(tempspice)
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os.remove(tempgds)
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def DRC(self):
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"""Checks DRC for a module"""
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if OPTS.check_lvsdrc:
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tempgds = OPTS.openram_temp + "/temp.gds"
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self.gds_write(tempgds)
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debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name))
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os.remove(tempgds)
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def LVS(self):
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"""Checks LVS for a module"""
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if OPTS.check_lvsdrc:
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tempspice = OPTS.openram_temp + "/temp.sp"
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tempgds = OPTS.openram_temp + "/temp.gds"
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self.sp_write(tempspice)
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self.gds_write(tempgds)
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debug.check(verify.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name))
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os.remove(tempspice)
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os.remove(tempgds)
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def __str__(self):
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""" override print function output """
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return "design: " + self.name
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def __repr__(self):
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""" override print function output """
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text="( design: " + self.name + " pins=" + str(self.pins) + " " + str(self.width) + "x" + str(self.height) + " )\n"
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for i in self.objs:
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text+=str(i)+",\n"
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for i in self.insts:
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text+=str(i)+",\n"
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return text
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