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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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722bc907c41d59252354de7ae223cc82428725ee
OpenRAM/compiler/pgates
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Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
..
pand2.py
pgate inputs and outputs are all on M1 for flexible via placement when using gates.
2018-11-28 12:42:29 -08:00
pbuf.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
pgate.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinv.py
Separated relative delay into rise/fall.
2018-11-14 23:34:53 -08:00
pinvbuf.py
Separated relative delay into rise/fall.
2018-11-14 23:34:53 -08:00
pnand2.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
pnand3.py
Separated relative delay into rise/fall.
2018-11-14 23:34:53 -08:00
pnor2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
precharge.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
ptx.py
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
single_level_column_mux.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
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