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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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71606e10976dee51914b7db208762cb4e788be5e
OpenRAM/compiler/characterizer
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Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure.
2018-07-27 14:06:59 -07:00
..
__init__.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Add read cycle to clear DOUT bus before each read measure.
2018-07-27 14:06:59 -07:00
lib.py
Fixed timing to be measured from positive clock edge since
2018-07-26 13:58:50 -07:00
setup_hold.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
stimuli.py
Split DATA into DIN and DOUT in characterizer
2018-07-11 14:19:09 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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