mirror of https://github.com/VLSIDA/OpenRAM.git
67 lines
2.0 KiB
Python
67 lines
2.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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from tech import cell_properties as props
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import bitcell_base
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class bitcell_1port(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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def __init__(self, name):
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super().__init__(name, prop=props.bitcell_1port)
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debug.info(2, "Create bitcell")
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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row_pins = ["wl"]
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return row_pins
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def get_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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return ["bl", "br"]
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def get_all_bl_names(self):
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""" Creates a list of all bl pins names """
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return ["bl"]
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def get_all_br_names(self):
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""" Creates a list of all br pins names """
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return ["br"]
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def get_bl_name(self, port=0):
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"""Get bl name"""
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debug.check(port == 0, "One port for bitcell only.")
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return "bl"
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def get_br_name(self, port=0):
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"""Get bl name"""
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debug.check(port == 0, "One port for bitcell only.")
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return "br"
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def get_wl_name(self, port=0):
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"""Get wl name"""
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debug.check(port == 0, "One port for bitcell only.")
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return "wl"
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def build_graph(self, graph, inst_name, port_nets):
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"""
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Adds edges based on inputs/outputs.
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Overrides base class function.
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"""
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self.add_graph_edges(graph, port_nets)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False |