mirror of https://github.com/VLSIDA/OpenRAM.git
130 lines
4.6 KiB
Python
130 lines
4.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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from tech import drc
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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class precharge_array(design.design):
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"""
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Dynamically generated precharge array of all bitlines. Cols is number
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of bit line columns, height is the height of the bit-cell array.
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"""
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def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br"):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
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self.columns = columns
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self.size = size
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def add_pins(self):
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"""Adds pins for spice file"""
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for i in range(self.columns):
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# These are outputs from the precharge only
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self.add_pin("bl_{0}".format(i), "OUTPUT")
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self.add_pin("br_{0}".format(i), "OUTPUT")
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self.add_pin("en_bar", "INPUT")
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self.add_pin("vdd", "POWER")
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_insts()
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def create_layout(self):
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self.width = self.columns * self.pc_cell.width
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self.height = self.pc_cell.height
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self.place_insts()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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self.pc_cell = factory.create(module_type="precharge",
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size=self.size,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.pc_cell)
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def add_layout_pins(self):
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self.add_layout_pin(text="en_bar",
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layer="m1",
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offset=self.pc_cell.get_pin("en_bar").ll(),
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width=self.width,
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height=drc("minwidth_m1"))
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for inst in self.local_insts:
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self.copy_layout_pin(inst, "vdd")
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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bl_pin = inst.get_pin("bl")
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self.add_layout_pin(text="bl_{0}".format(i),
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layer="m2",
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offset=bl_pin.ll(),
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width=drc("minwidth_m2"),
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height=bl_pin.height())
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br_pin = inst.get_pin("br")
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self.add_layout_pin(text="br_{0}".format(i),
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layer="m2",
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offset=br_pin.ll(),
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width=drc("minwidth_m2"),
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height=bl_pin.height())
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def create_insts(self):
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"""Creates a precharge array by horizontally tiling the precharge cell"""
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self.local_insts = []
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for i in range(self.columns):
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name = "pre_column_{0}".format(i)
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offset = vector(self.pc_cell.width * i, 0)
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inst = self.add_inst(name=name,
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mod=self.pc_cell,
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offset=offset)
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self.local_insts.append(inst)
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self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en_bar", "vdd"])
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def place_insts(self):
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""" Places precharge array by horizontally tiling the precharge cell"""
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from tech import cell_properties
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xoffset = 0
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for i in range(self.columns):
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tempx = xoffset
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if cell_properties.bitcell.mirror.y and (i + 1) % 2:
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mirror = "MY"
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tempx = tempx + self.pc_cell.width
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else:
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mirror = ""
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offset = vector(tempx, 0)
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self.local_insts[i].place(offset=offset, mirror=mirror)
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xoffset = xoffset + self.pc_cell.width
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def get_en_cin(self):
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"""Get the relative capacitance of all the clk connections in the precharge array"""
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#Assume single port
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precharge_en_cin = self.pc_cell.get_en_cin()
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return precharge_en_cin*self.columns
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