mirror of https://github.com/VLSIDA/OpenRAM.git
157 lines
6.4 KiB
Python
157 lines
6.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_mask_and_array(design.design):
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"""
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Array of AND gates to turn write mask signal on only when w_en is on.
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The write mask AND array goes between the write driver array and the sense amp array.
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"""
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def __init__(self, name, columns, word_size, write_size, port=0):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("write_size {0}".format(write_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.port = port
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self.words_per_row = int(columns / word_size)
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self.num_wmasks = int(word_size / write_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_and2_array()
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def create_layout(self):
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self.place_and2_array()
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spacing = self.wmask_en_len - self.and2.width
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self.width = (self.num_wmasks*self.and2.width) + ((self.num_wmasks-1)*spacing)
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self.height = self.and2.height
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_in_{}".format(bit),"INPUT")
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self.add_pin("en", "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_out_{}".format(bit),"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def add_modules(self):
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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# Assume stage effort of 3 to compute the size
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self.and2 = factory.create(module_type="pand2",
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size=self.write_size/4.0)
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self.add_mod(self.and2)
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def create_and2_array(self):
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self.and2_insts = {}
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for bit in range(self.num_wmasks):
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name = "and2_{}".format(bit)
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self.and2_insts[bit] = self.add_inst(name=name,
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mod=self.and2)
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self.connect_inst(["wmask_in_{}".format(bit),
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"en",
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"wmask_out_{}".format(bit),
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"vdd", "gnd"])
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def place_and2_array(self):
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# Place the write mask AND array at the start of each write driver enable length.
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# This ensures the write mask AND array will be directly under the corresponding write driver enable wire.
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# This is just used for measurements, so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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self.driver = factory.create(module_type="write_driver")
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if self.bitcell.width > self.driver.width:
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self.driver_spacing = self.bitcell.width
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else:
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self.driver_spacing = self.driver.width
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self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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debug.check(self.wmask_en_len >= self.and2.width,
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"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,self.wmask_en_len))
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for i in range(self.num_wmasks):
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base = vector(i * self.wmask_en_len, 0)
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self.and2_insts[i].place(base)
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def add_layout_pins(self):
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self.nand2 = factory.create(module_type="pnand2")
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supply_pin=self.nand2.get_pin("vdd")
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# Create the enable pin that connects all write mask AND array's B pins
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beg_en_pin = self.and2_insts[0].get_pin("B")
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end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
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if self.port % 2:
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# Extend metal3 to edge of AND array in multiport
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en_to_edge = self.and2.width - beg_en_pin.cx()
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self.add_layout_pin(text="en",
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layer="metal3",
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offset=beg_en_pin.bc(),
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width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
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else:
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self.add_layout_pin(text="en",
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layer="metal3",
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offset=beg_en_pin.bc(),
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width=end_en_pin.cx() - beg_en_pin.cx())
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for i in range(self.num_wmasks):
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# Copy remaining layout pins
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self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i))
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self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i))
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# Add via connections to metal3 for AND array's B pin
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en_pin = self.and2_insts[i].get_pin("B")
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=en_pin.center())
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=en_pin.center())
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self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))
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self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height))
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# Route power and ground rails together
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if i < self.num_wmasks-1:
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for n in ["gnd","vdd"]:
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pin = self.and2_insts[i].get_pin(n)
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next_pin = self.and2_insts[i+1].get_pin(n)
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self.add_path("metal1",[pin.center(),next_pin.center()])
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def get_cin(self):
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"""Get the relative capacitance of all the input connections in the bank"""
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# The enable is connected to an and2 for every row.
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return self.and2.get_cin() * len(self.and2_insts)
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